ecp5: Working on bitstream gen

Signed-off-by: David Shah <davey1576@gmail.com>

7 files changed, 585 insertions, 3 deletions

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 32063af6..f9dc10ec 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -40,7 +40,7 @@ set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /D_DEBUG /W4 /wd4100 /wd4244
 set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /W4 /wd4100 /wd4244 /wd4125 /wd4800 /wd4456 /wd4458 /wd4305 /wd4459 /wd4121 /wd4996 /wd4127")
 else()
 set(CMAKE_CXX_FLAGS_DEBUG "-Wall -fPIC -ggdb")
-set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O3 -g")
+set(CMAKE_CXX_FLAGS_RELEASE "-Wall -fPIC -O0 -ggdb")
 endif()
 set(CMAKE_DEFIN)
 
diff --git a/common/util.h b/common/util.h
index b492b98c..8f361dc8 100644
--- a/common/util.h
+++ b/common/util.h
@@ -96,6 +96,7 @@ inline const NetInfo *get_net_or_empty(const CellInfo *cell, const IdString port
     else
         return nullptr;
 };
+
 NEXTPNR_NAMESPACE_END
 
 #endif
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 5f9294c2..04bbc24f 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -33,6 +33,8 @@
 #include "log.h"
 #include "util.h"
 
+#define fmt_str(x) (static_cast<const std::ostringstream&>(std::ostringstream() << x).str())
+
 NEXTPNR_NAMESPACE_BEGIN
 
 // Convert an absolute wire name to a relative Trellis one
@@ -65,11 +67,97 @@ static std::vector<bool> int_to_bitvector(int val, int size)
     return bv;
 }
 
+// Get the PIO tile corresponding to a PIO bel
+static std::string get_pio_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
+{
+    static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
+    static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
+    static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"};
+    static const std::set<std::string> piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
+
+    std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+    if (bel.location.y == 0) {
+        if (pio_name == "PIOA") {
+            return chip.get_tile_by_position_and_type(0, bel.location.x, "PIOT0")->info.name;
+        } else if (pio_name == "PIOB") {
+            return chip.get_tile_by_position_and_type(0, bel.location.x + 1, "PIOT1")->info.name;
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    } else if (bel.location.y == ctx->chip_info->height - 1) {
+        if (pio_name == "PIOA") {
+            return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pioa_b)->info.name;
+        } else if (pio_name == "PIOB") {
+            return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, piob_b)->info.name;
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    } else if (bel.location.x == 0) {
+        return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_l)->info.name;
+    } else if (bel.location.x == ctx->chip_info->width - 1) {
+        return chip.get_tile_by_position_and_type(bel.location.y + 1, bel.location.x, pioabcd_r)->info.name;
+    } else {
+        NPNR_ASSERT_FALSE("bad PIO location");
+    }
+}
+
+// Get the PIC tile corresponding to a PIO bel
+static std::string get_pic_tile(Context *ctx, Trellis::Chip &chip, BelId bel)
+{
+    static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
+    static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
+    static const std::set<std::string> picab_r = {"PICR0", "PICR0_DQS2"};
+    static const std::set<std::string> piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"};
+
+    static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"};
+    static const std::set<std::string> picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"};
+
+    std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+    if (bel.location.y == 0) {
+        if (pio_name == "PIOA") {
+            return chip.get_tile_by_position_and_type(1, bel.location.x, "PICT0")->info.name;
+        } else if (pio_name == "PIOB") {
+            return chip.get_tile_by_position_and_type(1, bel.location.x + 1, "PICT1")->info.name;
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    } else if (bel.location.y == ctx->chip_info->height - 1) {
+        if (pio_name == "PIOA") {
+            return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, pica_b)->info.name;
+        } else if (pio_name == "PIOB") {
+            return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x + 1, picb_b)->info.name;
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    } else if (bel.location.x == 0) {
+        if (pio_name == "PIOA" || pio_name == "PIOB") {
+            return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_l)->info.name;
+        } else if (pio_name == "PIOC" || pio_name == "PIOD") {
+            return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_l)->info.name;
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    } else if (bel.location.x == ctx->chip_info->width - 1) {
+        if (pio_name == "PIOA" || pio_name == "PIOB") {
+            return chip.get_tile_by_position_and_type(bel.location.y, bel.location.x, picab_r)->info.name;
+        } else if (pio_name == "PIOC" || pio_name == "PIOD") {
+            return chip.get_tile_by_position_and_type(bel.location.y + 2, bel.location.x, piccd_r)->info.name;
+        } else {
+            NPNR_ASSERT_FALSE("bad PIO location");
+        }
+    } else {
+        NPNR_ASSERT_FALSE("bad PIO location");
+    }
+}
+
 void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file,
                      std::string bitstream_file)
 {
     Trellis::Chip empty_chip(ctx->getChipName());
     Trellis::ChipConfig cc;
+
+    std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
+
     if (!base_config_file.empty()) {
         std::ifstream config_file(base_config_file);
         if (!config_file) {
@@ -129,7 +217,23 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
             // TODO: CLKMUX, CEMUX, carry
         } else if (ci->type == ctx->id("TRELLIS_IO")) {
-            // TODO: IO config
+            std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+            std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
+            std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
+            std::string pio_tile = get_pio_tile(ctx, empty_chip, bel);
+            std::string pic_tile = get_pic_tile(ctx, empty_chip, bel);
+            cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+            cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
+            if (dir != "INPUT" && (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
+                // Tie tristate low if unconnected for outputs or bidir
+                std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
+                WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
+                PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
+                WireId cib_wire = ctx->getPipSrcWire(jpt_pip);
+                std::string cib_tile = empty_chip.get_tile_by_position_and_type(cib_wire.location.y, cib_wire.location.x, cib_tiles)->info.name;
+                std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
+                cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
+            }
         } else {
             NPNR_ASSERT_FALSE("unsupported cell type");
         }
diff --git a/ecp5/synth/.gitignore b/ecp5/synth/.gitignore
index 23844244..5b3bf578 100644
--- a/ecp5/synth/.gitignore
+++ b/ecp5/synth/.gitignore
@@ -1,2 +1 @@
-*.config
 *.bit
diff --git a/ecp5/synth/ulx3s.v b/ecp5/synth/ulx3s.v
new file mode 100644
index 00000000..7f0786f5
--- /dev/null
+++ b/ecp5/synth/ulx3s.v
@@ -0,0 +1,16 @@
+module top(input a_pin, output led_pin, output gpio0_pin);
+
+	wire a;
+	wire led;
+    wire gpio0;
+	(* BEL="X90/Y65/PIOB" *) (* IO_TYPE="LVCMOS33" *)
+	TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
+	(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
+	TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led), .T(t));
+	(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
+	TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0), .T(t));
+    assign led = !a;
+    wire t;
+    TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'h0000)) gnd (.F0(t));
+    TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
+endmodule
diff --git a/ecp5/synth/ulx3s.ys b/ecp5/synth/ulx3s.ys
new file mode 100644
index 00000000..d741c985
--- /dev/null
+++ b/ecp5/synth/ulx3s.ys
@@ -0,0 +1,9 @@
+read_verilog ulx3s.v
+read_verilog -lib cells.v
+synth -top top
+abc -lut 4
+techmap -map simple_map.v
+splitnets
+opt_clean
+stat
+write_json ulx3s.json
diff --git a/ecp5/synth/ulx3s_empty.config b/ecp5/synth/ulx3s_empty.config
new file mode 100644
index 00000000..8b641943
--- /dev/null
+++ b/ecp5/synth/ulx3s_empty.config
@@ -0,0 +1,453 @@
+.device LFE5U-45F
+
+.comment Lattice Semiconductor Corporation Bitstream
+.comment Version:         Diamond (64-bit) 3.10.0.111.2
+.comment Bitstream Status: Final Version 10.25
+.comment Design name: wire_impl1.ncd
+.comment Architecture: sa5p00
+.comment Part: LFE5U-45F-6CABGA381
+.comment Date: Sun Jul  8 15:46:42 2018
+.comment Rows: 9470
+.comment Cols: 846
+.comment Bits: 8011620
+.comment Readback:     Off
+.comment Security:     Off
+.comment Bitstream CRC: 0x66BA
+
+.tile CIB_R10C3:PVT_COUNT2
+unknown: F2B0
+unknown: F3B0
+unknown: F5B0
+unknown: F11B0
+unknown: F13B0
+
+.tile CIB_R5C1:CIB_PLL1
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R5C89:CIB_PLL1
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R70C3:CIB_PLL3
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile CIB_R70C42:VCIB_DCU0
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C43:VCIB_DCUA
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C44:VCIB_DCUB
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C45:VCIB_DCUC
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C46:VCIB_DCUD
+enum: CIB.JA1MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C47:VCIB_DCUF
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C48:VCIB_DCU3
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C49:VCIB_DCU2
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C50:VCIB_DCUG
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C51:VCIB_DCUH
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C52:VCIB_DCUI
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C53:VCIB_DCU1
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+
+
+.tile CIB_R70C69:VCIB_DCU0
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C6:CIB_EFB0
+enum: CIB.JB3MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C70:VCIB_DCUA
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C71:VCIB_DCUB
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C72:VCIB_DCUC
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C73:VCIB_DCUD
+enum: CIB.JA1MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C74:VCIB_DCUF
+enum: CIB.JA1MUX 0
+enum: CIB.JA3MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC2MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C75:VCIB_DCU3
+enum: CIB.JA5MUX 0
+enum: CIB.JA7MUX 0
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JC0MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC6MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C76:VCIB_DCU2
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C77:VCIB_DCUG
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C78:VCIB_DCUH
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C79:VCIB_DCUI
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB7MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD6MUX 0
+
+
+.tile CIB_R70C7:CIB_EFB1
+enum: CIB.JA3MUX 0
+enum: CIB.JA4MUX 0
+enum: CIB.JA5MUX 0
+enum: CIB.JA6MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB4MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JB6MUX 0
+enum: CIB.JC3MUX 0
+enum: CIB.JC4MUX 0
+enum: CIB.JC5MUX 0
+enum: CIB.JD3MUX 0
+enum: CIB.JD4MUX 0
+enum: CIB.JD5MUX 0
+
+
+.tile CIB_R70C80:VCIB_DCU1
+enum: CIB.JB1MUX 0
+enum: CIB.JB3MUX 0
+enum: CIB.JB5MUX 0
+enum: CIB.JD0MUX 0
+enum: CIB.JD2MUX 0
+
+
+.tile CIB_R70C87:CIB_PLL3
+enum: CIB.JA3MUX 0
+enum: CIB.JB3MUX 0
+
+
+.tile MIB_R10C40:CMUX_UL_0
+arc: G_DCS0CLK0 G_VPFN0000
+
+
+.tile MIB_R10C41:CMUX_UR_0
+arc: G_DCS0CLK1 G_VPFN0000
+
+
+.tile MIB_R58C40:CMUX_LL_0
+arc: G_DCS1CLK0 G_VPFN0000
+
+
+.tile MIB_R58C41:CMUX_LR_0
+arc: G_DCS1CLK1 G_VPFN0000
+
+
+.tile MIB_R71C4:EFB0_PICB0
+unknown: F54B1
+unknown: F56B1
+unknown: F82B1
+unknown: F94B1
+
+.tile MIB_R71C3:BANKREF8
+unknown: F18B0
+