diff options
| author | myrtle <gatecat@ds0.me> | 2023-01-04 20:01:05 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-04 20:01:05 +0100 |
| commit | a46afc6ff8aca9a4b9275b3385bfec70f008e10b (patch) | |
| tree | a7ecff72e6dac60690fc6cd0c60b6b4314e9b707 /ecp5/arch.cc | |
| parent | f89b959b5f56ba8d91e1e7f8a645b267a5a7bb89 (diff) | |
| parent | 8d8c244e007a5f2d937c569365785ae066c4ce5f (diff) | |
| download | nextpnr-a46afc6ff8aca9a4b9275b3385bfec70f008e10b.tar.gz nextpnr-a46afc6ff8aca9a4b9275b3385bfec70f008e10b.tar.bz2 nextpnr-a46afc6ff8aca9a4b9275b3385bfec70f008e10b.zip | |
Merge pull request #1076 from adamgreig/ecp5-dsp-remap
ECP5: Add DSP signal remapping
Diffstat (limited to 'ecp5/arch.cc')
| -rw-r--r-- | ecp5/arch.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index eb874704..a7041e04 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -634,6 +634,10 @@ bool Arch::place() for (auto &cell : cells) cell.second->belStrength = STRENGTH_LOCKED; + // Once placement is complete, DSP slices sharing a block may need + // CLK/CE/RST ports remapped to avoid conflicting assignments. + remap_dsp_blocks(); + getCtx()->settings[id_place] = 1; archInfoToAttributes(); |