| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add remapping of DSP clk/ce/rst signals in a block. | Adam Greig | 2023-01-04 | 1 | -0/+17 |
| * | ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels | gatecat | 2022-04-07 | 1 | -0/+10 |
| * | refactor: Use constids instead of id("..") | gatecat | 2022-02-16 | 1 | -0/+510 |
| * | ecp5: Add DCSC support | gatecat | 2021-07-06 | 1 | -0/+4 |
| * | Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui | Miodrag Milanovic | 2019-12-28 | 1 | -0/+8 |
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| | * | ecp5: Add constids for new timing cell types | David Shah | 2019-10-26 | 1 | -0/+8 |
| * | | add newline at eof | Miodrag Milanovic | 2019-12-28 | 1 | -1/+1 |
| * | | Add global wires | Miodrag Milanovic | 2019-12-15 | 1 | -1/+4 |
| * | | more new wires added | Miodrag Milanovic | 2019-12-14 | 1 | -0/+7 |
| * | | new wires in db | Miodrag Milanovic | 2019-12-13 | 1 | -1/+5 |
| * | | added siologic | Miodrag Milanovic | 2019-12-13 | 1 | -0/+1 |
| * | | Add many new wires | Miodrag Milanovic | 2019-12-13 | 1 | -0/+7 |
| * | | display horizontal wires, add some globals to list | Miodrag Milanovic | 2019-10-23 | 1 | -0/+2 |
| * | | Simplify layout of elements | Miodrag Milanovic | 2019-10-20 | 1 | -2/+0 |
| * | | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 1 | -0/+2 |
| * | | Less types needed | Miodrag Milanovic | 2019-10-20 | 1 | -16/+8 |
| * | | Added type to wire | Miodrag Milanovic | 2019-10-20 | 1 | -0/+19 |
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| * | ecp5: Add IDDR71B support | David Shah | 2019-10-09 | 1 | -0/+1 |
| * | ecp5: Preparations for new IO bels | David Shah | 2019-10-09 | 1 | -1/+5 |
| * | ecp5: Conservative analysis of comb DSP timing | David Shah | 2019-07-08 | 1 | -1/+8 |
| * | ecp5: Helper functions for DQS and ECLK | David Shah | 2019-02-24 | 1 | -0/+2 |
| * | ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGG | David Shah | 2019-02-08 | 1 | -1/+99 |
| * | ecp5: Add {S}IOLOGIC constids and cell | David Shah | 2018-12-12 | 1 | -0/+40 |
| * | ecp5: Adding real timing data to database | David Shah | 2018-11-16 | 1 | -2/+27 |
| * | ecp5: Adding ancillary DCU bels | David Shah | 2018-11-15 | 1 | -0/+7 |
| * | ecp5: Groundwork for DCU support | David Shah | 2018-11-15 | 1 | -0/+300 |
| * | ecp5: Add PLL support | David Shah | 2018-10-31 | 1 | -0/+23 |
| * | ecp5: Adding DSP support | David Shah | 2018-10-21 | 1 | -1/+616 |
| * | ecp5: Adding constids for blockram | David Shah | 2018-10-05 | 1 | -0/+118 |
| * | ecp5: Add DCC Bels, fix global router post-rebase | David Shah | 2018-09-29 | 1 | -0/+4 |
| * | ecp5: Update to use const IdStrings in place of PortPin/BelType | David Shah | 2018-08-08 | 1 | -0/+52 |
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index : iCE40/nextpnr | |
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