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| author | gatecat <gatecat@ds0.me> | 2021-12-14 09:03:50 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-14 09:03:50 +0000 |
| commit | 256134d6158b59831462f26f0011627eda10beb2 (patch) | |
| tree | 9d57a381245a647b9c06ebf2f3aaeee811581765 /ecp5/trellis_import.py | |
| parent | 73a7406211022a434ba2902afc3ccbe3dc6169b4 (diff) | |
| parent | f36188f2e18783ea692f8b6132712a0d1da6b6b7 (diff) | |
| download | nextpnr-256134d6158b59831462f26f0011627eda10beb2.tar.gz nextpnr-256134d6158b59831462f26f0011627eda10beb2.tar.bz2 nextpnr-256134d6158b59831462f26f0011627eda10beb2.zip | |
Merge pull request #870 from YosysHQ/gatecat/ecp5-lutperm
ecp5: LUT permutation support
Diffstat (limited to 'ecp5/trellis_import.py')
| -rwxr-xr-x | ecp5/trellis_import.py | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 2e76fb74..a586db7b 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -426,6 +426,8 @@ def write_database(dev_name, chip, ddrg, endianness): if cls == 1 and "PCS" in snk_name or "DCU" in snk_name or "DCU" in src_name: cls = 2 bba.u8(cls, "pip_type") + bba.u16(arc.lutperm_flags, "lutperm_flags") + bba.u16(0, "padding") if len(loctype.wires) > 0: for wire_idx in range(len(loctype.wires)): wire = loctype.wires[wire_idx] @@ -623,7 +625,7 @@ def main(): # print("Initialising chip...") chip = pytrellis.Chip(dev_names[args.device]) # print("Building routing graph...") - ddrg = pytrellis.make_dedup_chipdb(chip) + ddrg = pytrellis.make_dedup_chipdb(chip, include_lutperm_pips=True) max_row = chip.get_max_row() max_col = chip.get_max_col() process_timing_data() |