aboutsummaryrefslogtreecommitdiffstats
path: root/ecp5/trellis_import.py
Commit message (Expand)AuthorAgeFilesLines
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-1/+62
* ecp5: LUT permutation supportgatecat2021-12-131-1/+3
* ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-131-8/+10
* ecp5: Switch from RelPtr to RelSliceD. Shah2021-01-271-37/+28
* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-0/+2
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-5/+9
* ecp5: Add SPICB0 IO supportDavid Shah2020-01-201-1/+1
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-2/+6
|\
| * ecp5: Add constids for new timing cell typesDavid Shah2019-10-261-0/+2
| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-2/+4
* | Add global wiresMiodrag Milanovic2019-12-151-0/+9
* | more new wires addedMiodrag Milanovic2019-12-141-0/+24
* | add moreMiodrag Milanovic2019-12-131-0/+9
* | added siologicMiodrag Milanovic2019-12-131-0/+3
* | Add many new wiresMiodrag Milanovic2019-12-131-0/+21
* | display horizontal wires, add some globals to listMiodrag Milanovic2019-10-231-0/+3
* | Simplify layout of elementsMiodrag Milanovic2019-10-201-6/+6
* | more wires between switchboxesMiodrag Milanovic2019-10-201-0/+6
* | Less types neededMiodrag Milanovic2019-10-201-40/+16
* | Start adding visible wiresMiodrag Milanovic2019-10-201-0/+28
* | Added type to wireMiodrag Milanovic2019-10-201-0/+60
|/
* ecp5: Router performance improvementsDavid Shah2019-02-251-2/+8
* ecp5: Add DQS groupings to databaseDavid Shah2019-02-241-3/+14
* ecp5: Add 10% safety margin to pip delaysDavid Shah2018-11-161-2/+2
* ecp5: Fix db import, improve timing data debuggingDavid Shah2018-11-161-3/+11
* ecp5: Fix timing pip classesDavid Shah2018-11-161-1/+1
* ecp5: Fix timing data importDavid Shah2018-11-161-5/+16
* ecp5: Adding real timing data to databaseDavid Shah2018-11-161-31/+105
* ecp5: Groundwork for DCU supportDavid Shah2018-11-151-3/+8
* ecp5: Import SPINE data to databaseDavid Shah2018-09-291-1/+8
* ecp5: Add crude approximation of Pip delaysDavid Shah2018-08-191-2/+44
* ecp5: Update to use const IdStrings in place of PortPin/BelTypeDavid Shah2018-08-081-14/+12
* ecp5: Write tiletype names in correct orderDavid Shah2018-08-021-1/+1
* ecp5: Add tilemap to chip databaseDavid Shah2018-08-011-2/+17
* ecp5: Fix chipdb builderDavid Shah2018-07-271-1/+2
* ecp5: Add global network info to databaseDavid Shah2018-07-251-0/+18
* ecp5: Update trellis_import to use new bbasmDavid Shah2018-07-251-289/+42
* ecp5: Remove obsolete db entries, add Bel z-positionDavid Shah2018-07-231-15/+1
* ecp5: Adding new Bel pin APIDavid Shah2018-07-221-1/+11
* ecp5: Adding PIO data to chipdbDavid Shah2018-07-181-0/+78
* ecp5: Major improvements to Trellis importerDavid Shah2018-07-171-299/+71
* ecp5: Improving SLICE belDavid Shah2018-07-121-0/+29
* Deterministic chipdb blobsClifford Wolf2018-07-111-1/+1
* ecp5: Buttons workingDavid Shah2018-07-111-1/+1
* ecp5: Adding tiletypes to databaseDavid Shah2018-07-111-0/+5
* ecp5: Architecture fixesDavid Shah2018-07-111-1/+1
* ecp5: Add 25k databaseDavid Shah2018-07-111-3/+3
* ecp5: Adding complete binary blob writer to Trellis importerDavid Shah2018-07-111-32/+158
* ecp5: Starting to add BBA to importerDavid Shah2018-07-111-0/+313
* ecp5: Adding Bels to import scriptDavid Shah2018-07-111-10/+118
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-28 18:39:35 +0000