Merge pull request #459 from whitequark/better-chipdb

CMake: rewrite chipdb handling from ground up

1 files changed, 9 insertions, 5 deletions

diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index a21c4b3d..b591e09f 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -1,10 +1,7 @@
 #!/usr/bin/env python3
-import pytrellis
-import database
 import argparse
 import json
-import pip_classes
-import timing_dbs
+import sys
 from os import path
 
 location_types = dict()
@@ -17,8 +14,15 @@ parser = argparse.ArgumentParser(description="import ECP5 routing and bels from
 parser.add_argument("device", type=str, help="target device")
 parser.add_argument("-p", "--constids", type=str, help="path to constids.inc")
 parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
+parser.add_argument("-L", "--libdir", type=str, action="append", help="extra Python library path")
 args = parser.parse_args()
 
+sys.path += args.libdir
+import pytrellis
+import database
+import pip_classes
+import timing_dbs
+
 with open(args.gfxh) as f:
     state = 0
     for line in f:
@@ -437,7 +441,7 @@ def write_database(dev_name, chip, ddrg, endianness):
                 bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
                 if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
                     bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
-                else:                    
+                else:
                     bba.u32(0, "tile_wire")
                 bba.u32(len(wire.arcsUphill), "num_uphill")
                 bba.u32(len(wire.arcsDownhill), "num_downhill")