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| author | Adam Greig <adam@adamgreig.com> | 2022-11-09 02:44:37 +0000 |
|---|---|---|
| committer | Adam Greig <adam@adamgreig.com> | 2023-01-04 13:48:39 +0000 |
| commit | 174848b4b3bb84883c1623315ad10fdb5eb5185c (patch) | |
| tree | b8b83d487615e1ea00e7471bbf4dcfb97a57e536 /ecp5 | |
| parent | f89b959b5f56ba8d91e1e7f8a645b267a5a7bb89 (diff) | |
| download | nextpnr-174848b4b3bb84883c1623315ad10fdb5eb5185c.tar.gz nextpnr-174848b4b3bb84883c1623315ad10fdb5eb5185c.tar.bz2 nextpnr-174848b4b3bb84883c1623315ad10fdb5eb5185c.zip | |
Include ALU54B in cell types with wire location overrides
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch_place.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc index 3151cc3e..30ae9b1b 100644 --- a/ecp5/arch_place.cc +++ b/ecp5/arch_place.cc @@ -203,7 +203,7 @@ void Arch::setup_wire_locations() CellInfo *ci = cell.second.get(); if (ci->bel == BelId()) continue; - if (ci->type.in(id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) { + if (ci->type.in(id_ALU54B, id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) { for (auto &port : ci->ports) { if (port.second.net == nullptr) continue; |