ecp5: Adding tiletypes to database

Signed-off-by: David Shah <davey1576@gmail.com>

3 files changed, 19 insertions, 2 deletions

diff --git a/ecp5/arch.h b/ecp5/arch.h
index 029caef0..219a960e 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -102,6 +102,7 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
     int32_t num_location_types;
     RelPtr<LocationTypePOD> locations;
     RelPtr<int32_t> location_type;
+    RelPtr<RelPtr<char>> tiletype_names;
 });
 
 #if defined(_MSC_VER)
@@ -698,6 +699,11 @@ struct Arch : BaseCtx
         return range;
     }
 
+    std::string getPipTiletype(PipId pip) const
+    {
+        return chip_info->tiletype_names[locInfo(pip)->pip_data[pip.index].tile_type].get();
+    }
+
     BelId getPackagePinBel(const std::string &pin) const;
     std::string getBelPackagePin(BelId bel) const;
 
diff --git a/ecp5/main.cc b/ecp5/main.cc
index c16e23bb..6456a11e 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -33,6 +33,8 @@
 #include <iostream>
 
 #include "Database.hpp"
+#include "Chip.hpp"
+#include "Tile.hpp"
 
 #include "log.h"
 #include "nextpnr.h"
@@ -103,7 +105,7 @@ int main(int argc, char *argv[])
             return 1;
         }
 
-        Trellis::load_database(TRELLIS_ROOT"/database");
+        Trellis::load_database(TRELLIS_ROOT "/database");
 
         ArchArgs args;
         args.type = ArchArgs::LFE5U_25F;
@@ -147,9 +149,13 @@ int main(int argc, char *argv[])
                 log_error("Routing design failed.\n");
 
             // TEST BEGIN
+            Trellis::Chip c("LFE5U-25F");
             for (auto pip : ctx.getPips()) {
                 if (!ctx.checkPipAvail(pip)) {
-                    std::cout << ctx.getWireName(ctx.getPipSrcWire(pip)).str(&ctx) << " -> " << ctx.getWireName(ctx.getPipDstWire(pip)).str(&ctx) << std::endl;
+                    auto tile = c.get_tile_by_position_and_type(pip.location.y, pip.location.x, ctx.getPipTiletype(pip));
+                    std::cout << ctx.getWireName(ctx.getPipSrcWire(pip)).str(&ctx) << " -> "
+                              << ctx.getWireName(ctx.getPipDstWire(pip)).str(&ctx) << " [in tile "
+                              <<  tile->info.name << "]" << std::endl;
                 }
             }
             // TEST END
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index 62aa4d81..6ff929f7 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -592,6 +592,10 @@ def write_database(dev_name, endianness):
         for x in range(0, max_col+1):
             bba.u32(type_at_location[x, y], "loctype")
 
+    bba.l("tiletype_names", "RelPtr<char>")
+    for tt in tiletype_names:
+        bba.s(tt, "name")
+
     bba.l("chip_info")
     bba.u32(max_col + 1, "width")
     bba.u32(max_row + 1, "height")
@@ -599,6 +603,7 @@ def write_database(dev_name, endianness):
     bba.u32(len(location_types), "num_location_types")
     bba.r("locations", "locations")
     bba.r("location_types", "location_type")
+    bba.r("tiletype_names", "tiletype_names")
     bba.finalize()
     return bba