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| author | David Shah <dave@ds0.me> | 2019-02-12 16:01:31 +0000 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2019-02-24 10:28:25 +0100 |
| commit | 6e8fbe8cdfd0316ff42b2ccc277532970f05c1e0 (patch) | |
| tree | 83c484650dff681d19d670e0227f74d56b95670d /ecp5 | |
| parent | 4e49ab16259831cd40ecfb568d2e9c7d67cc932d (diff) | |
| download | nextpnr-6e8fbe8cdfd0316ff42b2ccc277532970f05c1e0.tar.gz nextpnr-6e8fbe8cdfd0316ff42b2ccc277532970f05c1e0.tar.bz2 nextpnr-6e8fbe8cdfd0316ff42b2ccc277532970f05c1e0.zip | |
ecp5: Add IDDRX2DQA support
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/pack.cc | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/ecp5/pack.cc b/ecp5/pack.cc index 01272a3d..c378a849 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -1856,6 +1856,36 @@ class Ecp5Packer process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270); pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO"; packed_cells.insert(cell.first); + } else if (ci->type == ctx->id("IDDRX2DQA")) { + CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O); + if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1) + log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n", + ci->name.c_str(ctx)); + CellInfo *iol; + if (pio_iologic.count(pio->name)) + iol = pio_iologic.at(pio->name); + else + iol = create_pio_iologic(pio, ci); + set_iologic_mode(iol, "MIDDRX_MODDRX"); + replace_port(ci, ctx->id("D"), iol, id_PADDI); + set_iologic_sclk(iol, ci, ctx->id("SCLK"), true); + set_iologic_eclk(iol, ci, id_ECLK); + set_iologic_lsr(iol, ci, ctx->id("RST"), true); + replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0); + replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1); + replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2); + replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3); + replace_port(ci, ctx->id("QWL"), iol, id_INFF); + iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED"); + iol->params[ctx->id("MIDDRX.MODE")] = "MIDDRX2"; + process_dqs_port(ci, pio, iol, id_DQSR90); + process_dqs_port(ci, pio, iol, id_RDPNTR2); + process_dqs_port(ci, pio, iol, id_RDPNTR1); + process_dqs_port(ci, pio, iol, id_RDPNTR0); + process_dqs_port(ci, pio, iol, id_WRPNTR2); + process_dqs_port(ci, pio, iol, id_WRPNTR1); + process_dqs_port(ci, pio, iol, id_WRPNTR0); + packed_cells.insert(cell.first); } } flush_cells(); |