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| author | David Shah <dave@ds0.me> | 2018-12-13 13:40:50 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-02-25 11:49:25 +0000 |
| commit | 998d055ea7f8bcc423d2aa2d75f5f27b6368666e (patch) | |
| tree | ca0aab09320b1608fa45c233e8988f4f2d69ba1b /ecp5 | |
| parent | e87fb696653262bea08caa100f0a5d4d31d2a310 (diff) | |
| download | nextpnr-998d055ea7f8bcc423d2aa2d75f5f27b6368666e.tar.gz nextpnr-998d055ea7f8bcc423d2aa2d75f5f27b6368666e.tar.bz2 nextpnr-998d055ea7f8bcc423d2aa2d75f5f27b6368666e.zip | |
ecp5: Speed up timing analysis
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 7 | ||||
| -rw-r--r-- | ecp5/archdefs.h | 2 | ||||
| -rw-r--r-- | ecp5/pack.cc | 3 |
3 files changed, 8 insertions, 4 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 7de5c7aa..0d6b6a55 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -602,7 +602,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort // Data for -8 grade if (cell->type == id_TRELLIS_SLICE) { - bool has_carry = str_or_default(cell->params, id("MODE"), "LOGIC") == "CCU2"; + bool has_carry = cell->sliceInfo.is_carry; if (fromPort == id_A0 || fromPort == id_B0 || fromPort == id_C0 || fromPort == id_D0 || fromPort == id_A1 || fromPort == id_B1 || fromPort == id_C1 || fromPort == id_D1 || fromPort == id_M0 || fromPort == id_M1 || fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) { @@ -639,7 +639,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in auto disconnected = [cell](IdString p) { return !cell->ports.count(p) || cell->ports.at(p).net == nullptr; }; clockInfoCount = 0; if (cell->type == id_TRELLIS_SLICE) { - int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); + int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1; if (port == id_CLK || port == id_WCK) return TMG_CLOCK_INPUT; if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 || @@ -782,8 +782,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.hold = getDelayFromNS(0); info.clockToQ = getDelayFromNS(0); if (cell->type == id_TRELLIS_SLICE) { - int sd0 = int_or_default(cell->params, id("REG0_SD"), 0), sd1 = int_or_default(cell->params, id("REG1_SD"), 0); - + int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1; if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 || port == id_WRE) { info.edge = RISING_EDGE; diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h index bfc5769b..d7ea0a8e 100644 --- a/ecp5/archdefs.h +++ b/ecp5/archdefs.h @@ -159,7 +159,9 @@ struct ArchCellInfo { bool using_dff; bool has_l6mux; + bool is_carry; IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode; + int sd0, sd1; } sliceInfo; }; diff --git a/ecp5/pack.cc b/ecp5/pack.cc index 64682fd2..db8c4002 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -2388,6 +2388,9 @@ void Arch::assignArchInfo() ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK")); ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR")); ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE")); + ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2"; + ci->sliceInfo.sd0 = int_or_default(ci->params, id("REG0_SD"), 0); + ci->sliceInfo.sd1 = int_or_default(ci->params, id("REG1_SD"), 0); ci->sliceInfo.has_l6mux = false; if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr && ci->ports[id_FXA].net->driver.port == id_OFX0) |