clang format

2 files changed, 132 insertions, 47 deletions

diff --git a/ecp5/gfx.h b/ecp5/gfx.h
index cc01ad9b..db618679 100644
--- a/ecp5/gfx.h
+++ b/ecp5/gfx.h
@@ -2209,33 +2209,6 @@ enum GfxTileWireId
     TILE_WIRE_R_HPBX1400,
     TILE_WIRE_R_HPBX1500,
 
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
     TILE_WIRE_JA0_CIBTEST,
     TILE_WIRE_JA1_CIBTEST,
     TILE_WIRE_JA2_CIBTEST,
@@ -2301,7 +2274,6 @@ enum GfxTileWireId
     TILE_WIRE_JQ6_CIBTEST,
     TILE_WIRE_JQ7_CIBTEST,
 
-
     TILE_WIRE_JA0_MULT9,
     TILE_WIRE_JA1_MULT9,
     TILE_WIRE_JA2_MULT9,
@@ -2428,7 +2400,6 @@ enum GfxTileWireId
     TILE_WIRE_JSROB7_MULT9,
     TILE_WIRE_JSROB8_MULT9,
 
-
     TILE_WIRE_JC0_PRADD9,
     TILE_WIRE_JC1_PRADD9,
     TILE_WIRE_JC2_PRADD9,
@@ -2516,7 +2487,6 @@ enum GfxTileWireId
     TILE_WIRE_JSROB7_PRADD9,
     TILE_WIRE_JSROB8_PRADD9,
 
-
     TILE_WIRE_JC0_PRADD18,
     TILE_WIRE_JC10_PRADD18,
     TILE_WIRE_JC11_PRADD18,
@@ -2676,7 +2646,6 @@ enum GfxTileWireId
     TILE_WIRE_JSROB8_PRADD18,
     TILE_WIRE_JSROB9_PRADD18,
 
-
     TILE_WIRE_JCE0_ALU24,
     TILE_WIRE_JCE1_ALU24,
     TILE_WIRE_JCE2_ALU24,
@@ -2826,19 +2795,6 @@ enum GfxTileWireId
     TILE_WIRE_JSIGNEDIA_ALU24,
     TILE_WIRE_JSIGNEDIB_ALU24,
 
-
-
-
-
-
-
-
-
-
-
-
-
-
     TILE_WIRE_G_BANK2ECLK0,
     TILE_WIRE_G_BANK2ECLK1,
     TILE_WIRE_G_BANK3ECLK0,
@@ -3163,9 +3119,6 @@ enum GfxTileWireId
     TILE_WIRE_G_VPFS1000,
     TILE_WIRE_G_VPFS1100,
 
-
-
-
     TILE_WIRE_BNK_ECLK0,
     TILE_WIRE_BNK_ECLK1,
     TILE_WIRE_BNK_INRD,
diff --git a/ecp5/synth/top.lpf b/ecp5/synth/top.lpf
new file mode 100644
index 00000000..dddc9552
--- /dev/null
+++ b/ecp5/synth/top.lpf
@@ -0,0 +1,132 @@
+BLOCK RESETPATHS;
+BLOCK ASYNCPATHS;
+LOCATE COMP "serial_tx" SITE "L4";
+IOBUF PORT "serial_tx" IO_TYPE=LVCMOS33;
+LOCATE COMP "serial_rx" SITE "M1";
+IOBUF PORT "serial_rx" IO_TYPE=LVCMOS33;
+LOCATE COMP "clk25" SITE "G2";
+IOBUF PORT "clk25" IO_TYPE=LVCMOS33;
+LOCATE COMP "rst" SITE "R1";
+IOBUF PORT "rst" IO_TYPE=LVCMOS33;
+LOCATE COMP "sdram_clock" SITE "F19";
+IOBUF PORT "sdram_clock" IO_TYPE=LVCMOS33;
+LOCATE COMP "wifi_gpio0" SITE "L2";
+IOBUF PORT "wifi_gpio0" IO_TYPE=LVCMOS33;
+LOCATE COMP "sdram_a[0]" SITE "M20";
+IOBUF PORT "sdram_a[0]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[0]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[1]" SITE "M19";
+IOBUF PORT "sdram_a[1]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[1]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[2]" SITE "L20";
+IOBUF PORT "sdram_a[2]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[2]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[3]" SITE "L19";
+IOBUF PORT "sdram_a[3]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[3]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[4]" SITE "K20";
+IOBUF PORT "sdram_a[4]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[4]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[5]" SITE "K19";
+IOBUF PORT "sdram_a[5]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[5]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[6]" SITE "K18";
+IOBUF PORT "sdram_a[6]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[6]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[7]" SITE "J20";
+IOBUF PORT "sdram_a[7]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[7]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[8]" SITE "J19";
+IOBUF PORT "sdram_a[8]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[8]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[9]" SITE "H20";
+IOBUF PORT "sdram_a[9]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[9]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[10]" SITE "N19";
+IOBUF PORT "sdram_a[10]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[10]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[11]" SITE "G20";
+IOBUF PORT "sdram_a[11]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[11]" SLEWRATE=FAST;
+LOCATE COMP "sdram_a[12]" SITE "G19";
+IOBUF PORT "sdram_a[12]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_a[12]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[0]" SITE "J16";
+IOBUF PORT "sdram_dq[0]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[0]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[1]" SITE "L18";
+IOBUF PORT "sdram_dq[1]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[1]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[2]" SITE "M18";
+IOBUF PORT "sdram_dq[2]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[2]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[3]" SITE "N18";
+IOBUF PORT "sdram_dq[3]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[3]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[4]" SITE "P18";
+IOBUF PORT "sdram_dq[4]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[4]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[5]" SITE "T18";
+IOBUF PORT "sdram_dq[5]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[5]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[6]" SITE "T17";
+IOBUF PORT "sdram_dq[6]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[6]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[7]" SITE "U20";
+IOBUF PORT "sdram_dq[7]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[7]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[8]" SITE "E19";
+IOBUF PORT "sdram_dq[8]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[8]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[9]" SITE "D20";
+IOBUF PORT "sdram_dq[9]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[9]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[10]" SITE "D19";
+IOBUF PORT "sdram_dq[10]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[10]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[11]" SITE "C20";
+IOBUF PORT "sdram_dq[11]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[11]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[12]" SITE "E18";
+IOBUF PORT "sdram_dq[12]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[12]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[13]" SITE "F18";
+IOBUF PORT "sdram_dq[13]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[13]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[14]" SITE "J18";
+IOBUF PORT "sdram_dq[14]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[14]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dq[15]" SITE "J17";
+IOBUF PORT "sdram_dq[15]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dq[15]" SLEWRATE=FAST;
+LOCATE COMP "sdram_we_n" SITE "T20";
+IOBUF PORT "sdram_we_n" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_we_n" SLEWRATE=FAST;
+LOCATE COMP "sdram_ras_n" SITE "R20";
+IOBUF PORT "sdram_ras_n" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_ras_n" SLEWRATE=FAST;
+LOCATE COMP "sdram_cas_n" SITE "T19";
+IOBUF PORT "sdram_cas_n" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_cas_n" SLEWRATE=FAST;
+LOCATE COMP "sdram_cs_n" SITE "P20";
+IOBUF PORT "sdram_cs_n" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_cs_n" SLEWRATE=FAST;
+LOCATE COMP "sdram_cke" SITE "F20";
+IOBUF PORT "sdram_cke" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_cke" SLEWRATE=FAST;
+LOCATE COMP "sdram_ba[0]" SITE "P19";
+IOBUF PORT "sdram_ba[0]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_ba[0]" SLEWRATE=FAST;
+LOCATE COMP "sdram_ba[1]" SITE "N20";
+IOBUF PORT "sdram_ba[1]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_ba[1]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dm[0]" SITE "U19";
+IOBUF PORT "sdram_dm[0]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dm[0]" SLEWRATE=FAST;
+LOCATE COMP "sdram_dm[1]" SITE "E20";
+IOBUF PORT "sdram_dm[1]" IO_TYPE=LVCMOS33;
+IOBUF PORT "sdram_dm[1]" SLEWRATE=FAST;
+
+FREQUENCY PORT "clk25" 25.0 MHz;
+
+FREQUENCY PORT "clk25" 25.0 MHz;
\ No newline at end of file