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| author | David Shah <dave@ds0.me> | 2018-11-15 17:39:13 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2018-11-16 13:26:28 +0000 |
| commit | cc746d888ba418db859a8acd3a3d3c4ddf48e294 (patch) | |
| tree | c4b9114e33a393063bf369ce5247a9e2b5a1a61e /ecp5 | |
| parent | 3ecd44074833de7f4785cd5fbd77c0570c818e8a (diff) | |
| download | nextpnr-cc746d888ba418db859a8acd3a3d3c4ddf48e294.tar.gz nextpnr-cc746d888ba418db859a8acd3a3d3c4ddf48e294.tar.bz2 nextpnr-cc746d888ba418db859a8acd3a3d3c4ddf48e294.zip | |
ecp5: Fix timing pip classes
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'ecp5')
| -rwxr-xr-x | ecp5/trellis_import.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 82d51076..d9892a28 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -222,7 +222,7 @@ def write_database(dev_name, chip, ddrg, endianness): loc = loc_with_type[arc_loctype] lt = ddrg.typeAtLocation[pytrellis.Location(loc[0] + rel.x, loc[1] + rel.y)] wire = ddrg.locationTypes[lt].wires[idx] - return "R{}C{}_{}".format(loc[0] + rel.x, loc[1] + rel.y, ddrg.to_str(wire.name)) + return "R{}C{}_{}".format(loc[1] + rel.y, loc[0] + rel.x, ddrg.to_str(wire.name)) bba = BinaryBlobAssembler() bba.pre('#include "nextpnr.h"') |