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authorDavid Shah <davey1576@gmail.com>2019-02-19 15:24:28 +0000
committerDavid Shah <davey1576@gmail.com>2019-02-24 10:28:25 +0100
commite50ab2106f9342b585377cf20f0b0c09125e3dbc (patch)
treeccf50f23f241193e74fd8fb29348dc35ae75e2de /ecp5
parent3b50b57f054dffba29031605a825e244c4b5327c (diff)
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ecp5: Fixes for litedram
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ecp5')
-rw-r--r--ecp5/bitstream.cc20
-rw-r--r--ecp5/pack.cc5
2 files changed, 17 insertions, 8 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 3fb2c5f1..f2b950bc 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -700,10 +700,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
iotype = "HSUL12";
break;
case IOVoltage::VCC_1V35:
- iotype = "SSTL135_I";
+ iotype = "SSTL18_I";
break;
case IOVoltage::VCC_1V5:
- iotype = "SSTL15_I";
+ iotype = "SSTL18_I";
break;
case IOVoltage::VCC_1V8:
iotype = "SSTL18_I";
@@ -816,13 +816,16 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
other = "PIOD";
else
log_error("cannot place differential IO at location %s\n", pio.c_str());
- // cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
- // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+ //cc.tiles[pio_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
+ //cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+ } else if (is_referenced(ioType_from_str(iotype))) {
+ cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
}
if (dir != "INPUT" &&
- (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
+ (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
+ (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() || ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
// Tie tristate low if unconnected for outputs or bidir
std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
@@ -837,12 +840,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
!is_referenced(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
}
- if (ci->attrs.count(ctx->id("SLEWRATE")))
+ if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype)))
cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
if (ci->attrs.count(ctx->id("PULLMODE")))
cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE"));
if (ci->attrs.count(ctx->id("DIFFRESISTOR")))
- cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR", str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
+ cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR",
+ str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
if (ci->attrs.count(ctx->id("TERMINATION"))) {
auto vccio = get_vccio(ioType_from_str(iotype));
switch (vccio) {
@@ -1268,7 +1272,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
} else if (ci->type == id_TRELLIS_ECLKBUF) {
} else if (ci->type == id_DQSBUFM) {
Loc loc = ctx->getBelLocation(ci->bel);
- bool l = loc.y < 10;
+ bool l = loc.x < 10;
std::string pic = l ? "PICL" : "PICR";
TileGroup tg;
tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 2, loc.x, pic + "1_DQS0"));
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 1b246ec1..a5cc5d98 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -1890,8 +1890,10 @@ class Ecp5Packer
}
replace_port(pio, id_I, pio, id_IOLDO);
set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
set_iologic_eclk(iol, ci, id_ECLK);
set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
@@ -1942,6 +1944,7 @@ class Ecp5Packer
set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
set_iologic_eclk(iol, ci, id_ECLK);
set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
@@ -1968,6 +1971,7 @@ class Ecp5Packer
set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
set_iologic_eclk(iol, ci, id_ECLK);
set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+ set_iologic_lsr(iol, ci, ctx->id("RST"), true);
replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
@@ -2033,6 +2037,7 @@ class Ecp5Packer
process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
iol->params[ctx->id("MTDDRX.MODE")] = "MTSHX2";
+ iol->params[ctx->id("MTDDRX.REGSET")] = "SET";
iol->params[ctx->id("MTDDRX.DQSW_INVERT")] = ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED";
iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270";
iol->params[ctx->id("IOLTOMUX")] = "TDDR";