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authorgatecat <gatecat@ds0.me>2021-07-12 11:40:23 +0100
committergatecat <gatecat@ds0.me>2021-07-12 11:40:23 +0100
commit8604b030088d9b0895a9384b21e37a97741a1ba2 (patch)
tree5c8dff1420bf5ac531afe24756c8ae371b9cd043 /fpga_interchange/arch_pack_io.cc
parent96a588505179c1d76a15119a6c8f719910f020cc (diff)
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interchange: Debug IO port validity check failures
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch_pack_io.cc')
-rw-r--r--fpga_interchange/arch_pack_io.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/fpga_interchange/arch_pack_io.cc b/fpga_interchange/arch_pack_io.cc
index b018c6bd..38b619a3 100644
--- a/fpga_interchange/arch_pack_io.cc
+++ b/fpga_interchange/arch_pack_io.cc
@@ -246,7 +246,8 @@ void Arch::pack_ports()
if (possible_site_types.empty()) {
if (getCtx()->verbose)
- log_info("Port '%s' has no possible site types, falling back to all types!\n", port_name.c_str(getCtx()));
+ log_info("Port '%s' has no possible site types, falling back to all types!\n",
+ port_name.c_str(getCtx()));
possible_site_types = package_pin_site_types;
}
@@ -316,6 +317,7 @@ void Arch::pack_ports()
for (CellInfo *cell : placed_cells) {
NPNR_ASSERT(cell->bel != BelId());
if (!isBelLocationValid(cell->bel)) {
+ explain_bel_status(cell->bel);
log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel));
}
}