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| author | gatecat <gatecat@ds0.me> | 2021-07-14 17:44:50 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-14 17:44:50 +0100 |
| commit | 084e15f9cf421786c3b0db8ea929211323bc4307 (patch) | |
| tree | 9e54a4ad4e54053a7cdad0a87e9a955292cfe2a3 /fpga_interchange/cell_parameters.h | |
| parent | 034467ff615494b2a74cee08081cb17edc9ea1a4 (diff) | |
| parent | 9190bda27d524dcf827208ea7cf40a198b3334c8 (diff) | |
| download | nextpnr-084e15f9cf421786c3b0db8ea929211323bc4307.tar.gz nextpnr-084e15f9cf421786c3b0db8ea929211323bc4307.tar.bz2 nextpnr-084e15f9cf421786c3b0db8ea929211323bc4307.zip | |
Merge pull request #762 from antmicro/testarch_timing
[interchange] Update chipdb and python-fpga-interchange versions
Diffstat (limited to 'fpga_interchange/cell_parameters.h')
0 files changed, 0 insertions, 0 deletions