Merge pull request #576 from litghost/add_cell_bel_pin_mapping

Complete FPGA interchange Arch to the point where it can route a wire

4 files changed, 34 insertions, 0 deletions

diff --git a/fpga_interchange/examples/lut/Makefile b/fpga_interchange/examples/lut/Makefile
new file mode 100644
index 00000000..54fc8994
--- /dev/null
+++ b/fpga_interchange/examples/lut/Makefile
@@ -0,0 +1,8 @@
+DESIGN := lut
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/lut.json: lut.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v
new file mode 100644
index 00000000..ca18e665
--- /dev/null
+++ b/fpga_interchange/examples/lut/lut.v
@@ -0,0 +1,5 @@
+module top(input i0, input i1, output o);
+
+assign o = i0 | i1;
+
+endmodule
diff --git a/fpga_interchange/examples/lut/lut.xdc b/fpga_interchange/examples/lut/lut.xdc
new file mode 100644
index 00000000..4f390f25
--- /dev/null
+++ b/fpga_interchange/examples/lut/lut.xdc
@@ -0,0 +1,7 @@
+set_property PACKAGE_PIN N16 [get_ports i0]
+set_property PACKAGE_PIN N15 [get_ports i1]
+set_property PACKAGE_PIN M17 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i0]
+set_property IOSTANDARD LVCMOS33 [get_ports i1]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl
new file mode 100644
index 00000000..1edd8bb7
--- /dev/null
+++ b/fpga_interchange/examples/lut/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog lut.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/lut.json