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| author | gatecat <gatecat@ds0.me> | 2021-03-17 14:05:49 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-17 14:05:49 +0000 |
| commit | 5feea4497f416eafdf54f34c2b9c67ddcef3f26f (patch) | |
| tree | e92427a879159b38441e6b3fc4f0e45ebc75e579 /fpga_interchange/examples/tests/wire | |
| parent | 701587241fb8d4b490c4998ab3f2590bc09d7f55 (diff) | |
| parent | 01a95faf211d5947415ed6a9ea2b1fbedf1074cd (diff) | |
| download | nextpnr-5feea4497f416eafdf54f34c2b9c67ddcef3f26f.tar.gz nextpnr-5feea4497f416eafdf54f34c2b9c67ddcef3f26f.tar.bz2 nextpnr-5feea4497f416eafdf54f34c2b9c67ddcef3f26f.zip | |
Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange
Add CMake infrastructure for fpga interchange
Diffstat (limited to 'fpga_interchange/examples/tests/wire')
| -rw-r--r-- | fpga_interchange/examples/tests/wire/CMakeLists.txt | 19 | ||||
| -rw-r--r-- | fpga_interchange/examples/tests/wire/run.tcl | 14 | ||||
| -rw-r--r-- | fpga_interchange/examples/tests/wire/wire.v | 5 | ||||
| -rw-r--r-- | fpga_interchange/examples/tests/wire/wire_arty.xdc | 5 | ||||
| -rw-r--r-- | fpga_interchange/examples/tests/wire/wire_basys3.xdc | 5 |
5 files changed, 48 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt new file mode 100644 index 00000000..59faf402 --- /dev/null +++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt @@ -0,0 +1,19 @@ +add_interchange_test( + name wire_basys3 + family ${family} + device xc7a35t + package cpg236 + tcl run.tcl + xdc wire_basys3.xdc + sources wire.v +) + +add_interchange_test( + name wire_arty + family ${family} + device xc7a35t + package csg324 + tcl run.tcl + xdc wire_arty.xdc + sources wire.v +) diff --git a/fpga_interchange/examples/tests/wire/run.tcl b/fpga_interchange/examples/tests/wire/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/wire/wire.v b/fpga_interchange/examples/tests/wire/wire.v new file mode 100644 index 00000000..429d05ff --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire.v @@ -0,0 +1,5 @@ +module top(input i, output o); + +assign o = i; + +endmodule diff --git a/fpga_interchange/examples/tests/wire/wire_arty.xdc b/fpga_interchange/examples/tests/wire/wire_arty.xdc new file mode 100644 index 00000000..c923f0fc --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire_arty.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N16 [get_ports i] +set_property PACKAGE_PIN N15 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i] +set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/tests/wire/wire_basys3.xdc b/fpga_interchange/examples/tests/wire/wire_basys3.xdc new file mode 100644 index 00000000..317d5acc --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire_basys3.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN V17 [get_ports i] +set_property PACKAGE_PIN U16 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i] +set_property IOSTANDARD LVCMOS33 [get_ports o] |