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| author | gatecat <gatecat@ds0.me> | 2021-03-31 15:14:51 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-31 15:14:51 +0100 |
| commit | ec98fee1eefd61d17ccfaf58bae72e1cc0f9e5e3 (patch) | |
| tree | 560c2e21d9a5c4bb5d55f7e62b77c141f39e651e /fpga_interchange/examples/tests | |
| parent | edecc06fcfbedf23773cd8ba04f1eb6f5bd64358 (diff) | |
| parent | 3678eff5dc13b301f7841d2079ba265bbe3fac2b (diff) | |
| download | nextpnr-ec98fee1eefd61d17ccfaf58bae72e1cc0f9e5e3.tar.gz nextpnr-ec98fee1eefd61d17ccfaf58bae72e1cc0f9e5e3.tar.bz2 nextpnr-ec98fee1eefd61d17ccfaf58bae72e1cc0f9e5e3.zip | |
Merge pull request #646 from YosysHQ/gatecat/nexus-cmake
fpga_interchange: Add CMake support for Nexus/prjoxide
Diffstat (limited to 'fpga_interchange/examples/tests')
5 files changed, 32 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/CMakeLists.txt b/fpga_interchange/examples/tests/CMakeLists.txt index 40ec8a75..f58adc70 100644 --- a/fpga_interchange/examples/tests/CMakeLists.txt +++ b/fpga_interchange/examples/tests/CMakeLists.txt @@ -4,3 +4,4 @@ add_subdirectory(counter) add_subdirectory(ram) add_subdirectory(ff) add_subdirectory(lut) +add_subdirectory(lut_nexus) diff --git a/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt b/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt new file mode 100644 index 00000000..1c65d87e --- /dev/null +++ b/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt @@ -0,0 +1,10 @@ +add_interchange_test( + name lut_nexus + family ${family} + device LIFCL-17 + package QFN72 + tcl run.tcl + xdc empty.xdc + sources lut.v + skip_dcp +) diff --git a/fpga_interchange/examples/tests/lut_nexus/empty.xdc b/fpga_interchange/examples/tests/lut_nexus/empty.xdc new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/fpga_interchange/examples/tests/lut_nexus/empty.xdc diff --git a/fpga_interchange/examples/tests/lut_nexus/lut.v b/fpga_interchange/examples/tests/lut_nexus/lut.v new file mode 100644 index 00000000..5913aff1 --- /dev/null +++ b/fpga_interchange/examples/tests/lut_nexus/lut.v @@ -0,0 +1,7 @@ +module top; + wire x, y; + (*keep*) + LUT4 lut_0(.A(x), .B(x), .C(x), .D(x), .Z(y)); + (*keep*) + LUT4 lut_1(.A(y), .B(y), .C(y), .D(y), .Z(x)); +endmodule
\ No newline at end of file diff --git a/fpga_interchange/examples/tests/lut_nexus/run.tcl b/fpga_interchange/examples/tests/lut_nexus/run.tcl new file mode 100644 index 00000000..4aa56c13 --- /dev/null +++ b/fpga_interchange/examples/tests/lut_nexus/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_nexus -noccu2 -nobram -nolutram -nowidelut + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) |