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| author | gatecat <gatecat@ds0.me> | 2021-05-13 11:31:03 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-21 10:00:35 +0100 |
| commit | bae83857a3bfe533a519c750f611e0e73c7ce4ef (patch) | |
| tree | 15e0603cb5112d071d41992533b866e998860539 /fpga_interchange/examples | |
| parent | 64f5b1d031960b779ca788d5fc92843c2213a045 (diff) | |
| download | nextpnr-bae83857a3bfe533a519c750f611e0e73c7ce4ef.tar.gz nextpnr-bae83857a3bfe533a519c750f611e0e73c7ce4ef.tar.bz2 nextpnr-bae83857a3bfe533a519c750f611e0e73c7ce4ef.zip | |
interchange: Add macro parameter mapping
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/examples')
| -rw-r--r-- | fpga_interchange/examples/tests/lutram/lutram.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/fpga_interchange/examples/tests/lutram/lutram.v b/fpga_interchange/examples/tests/lutram/lutram.v index be5728f8..f38197d4 100644 --- a/fpga_interchange/examples/tests/lutram/lutram.v +++ b/fpga_interchange/examples/tests/lutram/lutram.v @@ -7,7 +7,9 @@ module top ( input wire [15:0] sw, output wire [15:0] led ); - RAM128X1D ram_i ( + RAM128X1D #( + .INIT(128'hFFEEDDCCBBAA99887766554433221100) + ) ram_i ( .WCLK(clk), .A(sw[6:0]), .DPRA(sw[13:7]), |