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authorKeith Rothman <537074+litghost@users.noreply.github.com>2021-03-24 16:25:15 -0700
committerKeith Rothman <537074+litghost@users.noreply.github.com>2021-03-25 17:20:13 -0700
commit91ca5f110bdea0dbf1b6183d8129c3ea7b0c71c6 (patch)
treeab411c5dfb8543540da838991a454807670d96eb /fpga_interchange/site_arch.cc
parent5dda3a14ffd962407217cff4bb2859bebc503b8b (diff)
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Re-work LUT mapping logic to only put VCC pins when required.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/site_arch.cc')
-rw-r--r--fpga_interchange/site_arch.cc26
1 files changed, 26 insertions, 0 deletions
diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc
index 43792eda..711bef44 100644
--- a/fpga_interchange/site_arch.cc
+++ b/fpga_interchange/site_arch.cc
@@ -125,6 +125,7 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
// Create list of out of site sources and sinks.
+ bool have_vcc_pins = false;
for (CellInfo *cell : site_info->cells_in_site) {
for (const auto &pin_pair : cell->cell_bel_pins) {
const PortInfo &port = cell->ports.at(pin_pair.first);
@@ -132,6 +133,10 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
nets.emplace(port.net, SiteNetInfo{port.net});
}
}
+
+ if (!cell->lut_cell.vcc_pins.empty()) {
+ have_vcc_pins = true;
+ }
}
for (auto &net_pair : nets) {
@@ -222,6 +227,27 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
}
}
+ IdString vcc_net_name(ctx->chip_info->constants->vcc_net_name);
+ NetInfo *vcc_net = ctx->nets.at(vcc_net_name).get();
+ auto iter = nets.find(vcc_net);
+ if (iter == nets.end() && have_vcc_pins) {
+ // VCC net isn't present, add it.
+ SiteNetInfo net_info;
+ net_info.net = vcc_net;
+ net_info.driver.type = SiteWire::OUT_OF_SITE_SOURCE;
+ net_info.driver.net = vcc_net;
+ auto result = nets.emplace(vcc_net, net_info);
+ NPNR_ASSERT(result.second);
+ iter = result.first;
+ }
+
+ for (CellInfo *cell : site_info->cells_in_site) {
+ for (IdString vcc_pin : cell->lut_cell.vcc_pins) {
+ SiteWire wire = getBelPinWire(cell->bel, vcc_pin);
+ iter->second.users.emplace(wire);
+ }
+ }
+
for (auto &net_pair : nets) {
SiteNetInfo *net_info = &net_pair.second;
auto result = wire_to_nets.emplace(net_info->driver, SiteNetMap{net_info, 1});