| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added fallback to VCC as the preferred constant if the architecture does not ... | Maciej Kurc | 2022-05-12 | 1 | -1/+6 |
| * | Generalized representation of unused LUT pins connections | Maciej Kurc | 2022-05-11 | 1 | -10/+66 |
| * | refactor: New NetInfo and CellInfo constructors | gatecat | 2022-02-16 | 1 | -2/+2 |
| * | interchange: Cope with undriven nets in more places | gatecat | 2021-06-14 | 1 | -1/+4 |
| * | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -1/+1 |
| * | interchange: Don't error out on missing cell ports | gatecat | 2021-05-21 | 1 | -0/+2 |
| * | [interchange] Fix invalid use of local variables due to refactoring. | Keith Rothman | 2021-04-06 | 1 | -0/+3 |
| * | [interchange] Fix missing inline methods in site_arch.impl.h | Keith Rothman | 2021-04-06 | 1 | -8/+0 |
| * | Implement debugging tools for site router. | Keith Rothman | 2021-03-25 | 1 | -10/+36 |
| * | Re-work LUT mapping logic to only put VCC pins when required. | Keith Rothman | 2021-03-25 | 1 | -0/+26 |
| * | Rework FPGA interchange site router. | Keith Rothman | 2021-03-22 | 1 | -0/+376 |
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index : iCE40/nextpnr | |
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