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| author | gatecat <gatecat@ds0.me> | 2022-02-18 12:07:49 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-18 12:07:49 +0000 |
| commit | 347ba3afb3f541edc594c8bc276cce481c7a7e03 (patch) | |
| tree | 28483964fb3c92bc104ab6162d1c9196651ced26 /fpga_interchange/site_router.cc | |
| parent | 61d1db16be2c68cf6ae8b4d2ff3266b5c7086ad2 (diff) | |
| parent | 6a32aca4ac8705b637943c236cedd2f36422fb21 (diff) | |
| download | nextpnr-347ba3afb3f541edc594c8bc276cce481c7a7e03.tar.gz nextpnr-347ba3afb3f541edc594c8bc276cce481c7a7e03.tar.bz2 nextpnr-347ba3afb3f541edc594c8bc276cce481c7a7e03.zip | |
Merge pull request #919 from YosysHQ/gatecat/netlist-iii
refactor: New member functions to replace design_utils
Diffstat (limited to 'fpga_interchange/site_router.cc')
| -rw-r--r-- | fpga_interchange/site_router.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 08e950e2..4e3d460a 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -953,7 +953,7 @@ static void apply_constant_routing(Context *ctx, const SiteArch &site_arch, NetI new_cell->belStrength = STRENGTH_PLACER; ctx->tileStatus.at(inverting_bel.tile).boundcells[inverting_bel.index] = new_cell; - connect_port(ctx, net_before_inverter, new_cell, id_I); + new_cell->connectPort(id_I, net_before_inverter); // The original BEL pin is now routed, but only through the inverter. // Because the cell/net model doesn't allow for multiple source pins |