Merge pull request #604 from litghost/add_counter_test

Add counter test for FPGA interchange

1 files changed, 31 insertions, 6 deletions

diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index 7232b635..9d4fc57c 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -697,7 +697,7 @@ bool route_site(const Context *ctx, SiteInformation *site_info)
         // The simplistic solution (only select when 1 solution is available)
         // will likely solve initial problems.  Once that is show to be wrong,
         // come back with something more general.
-        NPNR_ASSERT(false);
+        return false;
 
     } while (!wire_to_expansion.empty());
 
@@ -747,17 +747,42 @@ bool SiteRouter::checkSiteRouting(const Context *ctx, const TileStatus &tile_sta
             return site_ok;
         }
     }
-    //
+
     // FIXME: Populate "consumed_wires" with all VCC/GND tied in the site.
     // This will allow route_site to leverage site local constant sources.
     //
     // FIXME: Handle case where a constant is requested, but use of an
     // inverter is possible. This is the place to handle "bestConstant"
     // (e.g. route VCC's over GND's, etc).
-    //
-    // FIXME: Enable some LUT rotation!
-    // Default cell/bel pin map always uses high pins, which will generate
-    // conflicts where there are none!!!
+    auto tile_type_idx = ctx->chip_info->tiles[tile].type;
+    const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(tile_type_idx);
+    std::vector<LutMapper> lut_mappers;
+    lut_mappers.reserve(lut_elements.size());
+    for (size_t i = 0; i < lut_elements.size(); ++i) {
+        lut_mappers.push_back(LutMapper(lut_elements[i]));
+    }
+
+    for (CellInfo *cell : cells_in_site) {
+        if (cell->lut_cell.pins.empty()) {
+            continue;
+        }
+
+        BelId bel = cell->bel;
+        const auto &bel_data = bel_info(ctx->chip_info, bel);
+        if (bel_data.lut_element != -1) {
+            lut_mappers[bel_data.lut_element].cells.push_back(cell);
+        }
+    }
+
+    for (LutMapper lut_mapper : lut_mappers) {
+        if (lut_mapper.cells.empty()) {
+            continue;
+        }
+
+        if (!lut_mapper.remap_luts(ctx)) {
+            return false;
+        }
+    }
 
     SiteInformation site_info(ctx, cells_in_site);