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| author | gatecat <gatecat@ds0.me> | 2021-05-21 11:05:57 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-05-21 11:05:57 +0100 |
| commit | e19d44ee209733d203175602d34eeba953ab910b (patch) | |
| tree | 2887f9d79fe62cfd39fe17deec8068065aa8ce62 /fpga_interchange/site_router.cc | |
| parent | 81818fd38c5405005305d1b8354eb75beb8dc18d (diff) | |
| parent | ff48ad83beabb18c8fdcab41c54dc320326b012e (diff) | |
| download | nextpnr-e19d44ee209733d203175602d34eeba953ab910b.tar.gz nextpnr-e19d44ee209733d203175602d34eeba953ab910b.tar.bz2 nextpnr-e19d44ee209733d203175602d34eeba953ab910b.zip | |
Merge pull request #686 from YosysHQ/gatecat/interchange-macro
interchange: Add macro expansion
Diffstat (limited to 'fpga_interchange/site_router.cc')
| -rw-r--r-- | fpga_interchange/site_router.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index f4d65958..69bd366f 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -59,8 +59,7 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info) BelId bel = cell->bel; for (const auto &pin_pair : cell->cell_bel_pins) { if (!cell->ports.count(pin_pair.first)) - log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx), - pin_pair.first.c_str(ctx)); + continue; const PortInfo &port = cell->ports.at(pin_pair.first); NPNR_ASSERT(port.net != nullptr); |