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authorAlessandro Comodi <acomodi@antmicro.com>2021-03-19 17:38:45 +0100
committerAlessandro Comodi <acomodi@antmicro.com>2021-03-23 20:36:23 +0100
commit4812092cdbda0da395b8df55eaa65c29ec421b8b (patch)
tree09d7c86edc646beb250ac69e9b95f741a30eaaaa /fpga_interchange
parent658dadaa70746940003f01ac37a65e64a0b0584d (diff)
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fpga_interchange: add test data for new architectures
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange')
-rw-r--r--fpga_interchange/examples/devices/xc7a100t/test_data.yaml36
-rw-r--r--fpga_interchange/examples/devices/xc7a200t/test_data.yaml36
-rw-r--r--fpga_interchange/examples/devices/xc7z010/test_data.yaml36
3 files changed, 108 insertions, 0 deletions
diff --git a/fpga_interchange/examples/devices/xc7a100t/test_data.yaml b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml
new file mode 100644
index 00000000..268d180a
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a100t/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+ - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+ dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+ - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+ - INT_R_X3Y145/GND_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+ - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+ - INT_R_X3Y145/VCC_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+ - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+ - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+ - bel: SLICE_X15Y93.SLICEL/D6LUT
+ pin: A3
+ wire: SLICE_X15Y93.SLICEL/D3
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+ pin: G
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+ pin: P
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/devices/xc7a200t/test_data.yaml b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml
new file mode 100644
index 00000000..268d180a
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7a200t/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+ - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
+ dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+ - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+ - INT_R_X3Y145/GND_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+ - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+ - INT_R_X3Y145/VCC_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+ - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+ - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+ - bel: SLICE_X15Y93.SLICEL/D6LUT
+ pin: A3
+ wire: SLICE_X15Y93.SLICEL/D3
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+ pin: G
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+ pin: P
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/devices/xc7z010/test_data.yaml b/fpga_interchange/examples/devices/xc7z010/test_data.yaml
new file mode 100644
index 00000000..dbc95845
--- /dev/null
+++ b/fpga_interchange/examples/devices/xc7z010/test_data.yaml
@@ -0,0 +1,36 @@
+pip_test:
+ - src_wire: CLBLM_L_X8Y69/CLBLM_L_D3
+ dst_wire: SLICE_X11Y69.SLICEL/D3
+pip_chain_test:
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - TIEOFF_X9Y69.TIEOFF/$GND_SITE_WIRE
+ - TIEOFF_X9Y69.TIEOFF/HARD0GND_HARD0
+ - INT_L_X8Y69/GND_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - TIEOFF_X9Y69.TIEOFF/$VCC_SITE_WIRE
+ - TIEOFF_X9Y69.TIEOFF/HARD1VCC_HARD1
+ - INT_L_X8Y69/VCC_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - SLICE_X11Y69.SLICEL/$VCC_SITE_WIRE
+ - SLICE_X11Y69.SLICEL/CEUSEDVCC_HARD1
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - SLICE_X11Y69.SLICEL/$GND_SITE_WIRE
+ - SLICE_X11Y69.SLICEL/SRUSEDGND_HARD0
+bel_pin_test:
+ - bel: SLICE_X14Y63.SLICEL/D6LUT
+ pin: A3
+ wire: SLICE_X14Y63.SLICEL/D3
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+ pin: G
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+ pin: P
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE