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authorAlessandro Comodi <acomodi@antmicro.com>2021-05-19 18:47:05 +0200
committerAlessandro Comodi <acomodi@antmicro.com>2021-05-19 18:48:54 +0200
commit84359f39c5e63770e9a58e87edbbc167f2c394b9 (patch)
tree2f8e7e2d2f5ee4e1e779dc94519230f1c30bfa4d /fpga_interchange
parent5a41d2070c8a7c065d4e3fbfb70b3a3fbd19b319 (diff)
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interchange: phys: add site instance idstr for pseudo tile PIPs
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange')
-rw-r--r--fpga_interchange/fpga_interchange.cpp19
1 files changed, 19 insertions, 0 deletions
diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp
index 60331382..cf89ef1c 100644
--- a/fpga_interchange/fpga_interchange.cpp
+++ b/fpga_interchange/fpga_interchange.cpp
@@ -91,6 +91,25 @@ static PhysicalNetlist::PhysNetlist::RouteBranch::Builder emit_branch(
pip_obj.setForward(true);
pip_obj.setIsFixed(pip_place_strength.at(pip) >= STRENGTH_FIXED);
+ // If this is a pseudo PIP, get its name
+ if (pip_data.pseudo_cell_wires.size() != 0) {
+ for (int32_t wire_index : pip_data.pseudo_cell_wires) {
+ const TileWireInfoPOD &wire_data = tile_type.wire_data[wire_index];
+
+ if (wire_data.site == -1) {
+ continue;
+ }
+
+ const SiteInstInfoPOD & site_data = site_inst_info(ctx->chip_info, pip.tile, wire_data.site);
+ std::string site_name = site_data.site_name.get();
+ int site_idx = strings->get_index(site_name);
+ pip_obj.setSite(site_idx);
+
+ // It is assumed that a pseudo PIP traverses one site only
+ break;
+ }
+ }
+
return branch;
} else {
BelId bel;