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authorDavid Shah <dave@ds0.me>2019-03-31 17:54:52 +0100
committerDavid Shah <dave@ds0.me>2019-04-02 15:30:01 +0100
commit50fd8aa01fde3426ff74fcf9b0126a24f279efca (patch)
treeddb2c33d65c977b656406d4a90827b959672bf83 /generic
parentfd3ad755988ee185427479595a8c368c3f1b9519 (diff)
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generic: Place a single SLICE
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'generic')
-rw-r--r--generic/arch_pybindings.cc10
-rw-r--r--generic/examples/simple.py3
-rw-r--r--generic/examples/simple.v15
3 files changed, 24 insertions, 4 deletions
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index 407dc4d4..014b7758 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -174,12 +174,14 @@ void arch_wrap_python()
pass_through<DecalXY>>::def_wrap(ctx_cls, "setGroupDecal", (arg("group"), "decalxy"));
fn_wrapper_3a_v<Context, decltype(&Context::setWireAttr), &Context::setWireAttr, conv_from_str<DecalId>,
- conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr", (arg("wire"), "key", "value"));
+ conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setWireAttr",
+ (arg("wire"), "key", "value"));
fn_wrapper_3a_v<Context, decltype(&Context::setBelAttr), &Context::setBelAttr, conv_from_str<DecalId>,
- conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr", (arg("bel"), "key", "value"));
+ conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setBelAttr",
+ (arg("bel"), "key", "value"));
fn_wrapper_3a_v<Context, decltype(&Context::setPipAttr), &Context::setPipAttr, conv_from_str<DecalId>,
- conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr", (arg("pip"), "key", "value"));
-
+ conv_from_str<IdString>, pass_through<std::string>>::def_wrap(ctx_cls, "setPipAttr",
+ (arg("pip"), "key", "value"));
WRAP_MAP_UPTR(CellMap, "IdCellMap");
WRAP_MAP_UPTR(NetMap, "IdNetMap");
diff --git a/generic/examples/simple.py b/generic/examples/simple.py
new file mode 100644
index 00000000..da41dc5b
--- /dev/null
+++ b/generic/examples/simple.py
@@ -0,0 +1,3 @@
+ctx.addBel(name="SLICE_X1Y1", type="SLICE_LUT4", loc=Loc(1, 1, 0), gb=False)
+ctx.addBel(name="IO0_I", type="$nextpnr_ibuf", loc=Loc(0, 0, 0), gb=False)
+ctx.addBel(name="IO1_O", type="$nextpnr_obuf", loc=Loc(1, 0, 0), gb=False) \ No newline at end of file
diff --git a/generic/examples/simple.v b/generic/examples/simple.v
new file mode 100644
index 00000000..6d337101
--- /dev/null
+++ b/generic/examples/simple.v
@@ -0,0 +1,15 @@
+(* blackbox *)
+module SLICE_LUT4(
+ input I0, I1, I2, I3,
+ input CLK,
+ output Q
+);
+parameter INIT = 16'h0000;
+parameter FF_USED = 1'b0;
+endmodule
+
+module top(input a, output q);
+
+SLICE_LUT4 sl_i(.I0(a), .Q(q));
+
+endmodule \ No newline at end of file