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authorPepijn de Vos <pepijndevos@gmail.com>2022-07-02 13:29:44 +0200
committerPepijn de Vos <pepijndevos@gmail.com>2022-07-02 13:29:44 +0200
commit0641ff47d9c437c02d77363d568b106c4ceae155 (patch)
tree0c2fb9f751004c7dcad0c7c618d3d6dd6b2cf0e3 /gowin/arch.h
parentb7992ec7724000f813ab053ac6042326f3795471 (diff)
parentb4337d99fde46abe85cab8bdf98a681eefe1f3e1 (diff)
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Merge branch 'master' into shadowram
Diffstat (limited to 'gowin/arch.h')
-rw-r--r--gowin/arch.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/gowin/arch.h b/gowin/arch.h
index c13cdf09..cd20f28a 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -459,6 +459,9 @@ struct Arch : BaseArch<ArchRanges>
void assignArchInfo() override;
bool cellsCompatible(const CellInfo **cells, int count) const;
bool haveBelType(int x, int y, IdString bel_type);
+ bool allocate_longwire(NetInfo *ni, int lw_idx = -1);
+ void fix_longwire_bels();
+
// chip db version
unsigned int const chipdb_version = 1;
@@ -475,6 +478,9 @@ struct Arch : BaseArch<ArchRanges>
// XXX GW1NR-9 iobuf quirk
bool gw1n9_quirk = false;
+ // 8 Long wires
+ uint8_t avail_longwires = 0xff;
+
// Permissible combinations of modes in a single slice
std::map<const IdString, IdString> dff_comp_mode;
};
@@ -488,7 +494,9 @@ enum
lutram_0_z = 30, // start Z for the IOLOGIC bels
vcc_0_z = 277, // virtual VCC bel Z
gnd_0_z = 278, // virtual VSS bel Z
- osc_z = 280 // Z for the oscillator bels
+ osc_z = 280, // Z for the oscillator bels
+ bufs_0_z = 281, // Z for long wire buffer bel
+ free_z = 289 // Must be the last, one can use z starting from this value, adjust accordingly.
};
}