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* gowin: add a common mechanism for placing portsYRabbit2023-04-201-0/+2
* gowin: Remove inherited code for ODDR(c)YRabbit2023-04-141-1/+0
* gowin: implement IDES16 and OSER16 primitivesYRabbit2023-04-121-1/+5
* gowin: Add support for OSER primitivesYRabbit2023-03-231-10/+19
* gowin: Proper use of the C++ mechanismsYRabbit2023-01-301-9/+7
* gowin: Add PLL support for the GW1NR-9 chipYRabbit2023-01-301-0/+9
* gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-261-1/+1
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-181-1/+6
* gowin: improve clock wire routingYRabbit2022-12-301-0/+1
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-071-1/+1
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| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-071-1/+1
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-071-1/+1
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| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-1/+1
* | gowin: add PLL pins processingYRabbit2022-12-041-0/+4
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* gowin: add information about pin configurationsYRabbit2022-11-251-2/+9
* gowin: add initial PLL supportYRabbit2022-11-101-1/+3
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-191-1/+1
* gowin: Remove unnecessary functionsYRabbit2022-07-051-5/+1
* Merge branch 'master' into clock-wipYRabbit2022-07-051-0/+1
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| * Merge branch 'master' into shadowramPepijn de Vos2022-07-021-1/+9
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| * | lutram actually PnRsPepijn de Vos2022-06-061-1/+0
| * | WIP shadowramPepijn de Vos2022-06-051-0/+2
* | | gowin: Let the placer know about global networksYRabbit2022-07-041-0/+14
* | | gowin: add a separate router for the clocksYRabbit2022-06-231-0/+1
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* | gowin: Add support for long wiresYRabbit2022-05-271-1/+9
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* gowin: handle the GW1N-9 feature.YRabbit2022-04-031-0/+2
* gowin: Fix z-index of oscillatorTim Pambor2022-03-301-1/+2
* gowin: Consider the peculiarity of GW1BR-9CYRabbit2022-03-261-0/+3
* gowin: add support for ODDR primitiveYRabbit2022-03-151-4/+13
* refactor: Use constids instead of id("..")gatecat2022-02-161-1/+1
* gowin: Add GUI.YRabbit2022-01-291-8/+21
* gowin: Initializing the grid dimensionsYRabbit2021-12-261-1/+1
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
* gowin: Check the chipdb versionYRabbit2021-11-071-0/+2
* gowin: Use speed from chip base.YRabbit2021-11-051-2/+1
* gowin: Add partnumbers and packages to the chipdbYRabbit2021-11-041-1/+9
* gowin: add support for wide LUTs.YRabbit2021-10-071-0/+3
* gowin: Add constraints on primitive placement.YRabbit2021-08-311-0/+3
* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
* Using hashlib in archesgatecat2021-06-021-25/+12
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-4/+15
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-8/+8
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-19/+11
* gowin: Use base bel bucket/cell type methodsgatecat2021-02-171-5/+1
* Remove isValidBelForCellgatecat2021-02-161-1/+0
* Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+2
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
* gowin: Switch to BaseArchD. Shah2021-02-051-110/+105
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