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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-18 13:35:25 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-18 13:35:25 +0200 |
| commit | ad18cdb08787c4ecc88edaec353a96f59135c62d (patch) | |
| tree | 3a13281f1adea564d0848d93ef4bcf4d1d4bf952 /ice40/arch_place.cc | |
| parent | 2f5e9542c2d9132b2c01d4dbc8c4d2dff97c60cf (diff) | |
| download | nextpnr-ad18cdb08787c4ecc88edaec353a96f59135c62d.tar.gz nextpnr-ad18cdb08787c4ecc88edaec353a96f59135c62d.tar.bz2 nextpnr-ad18cdb08787c4ecc88edaec353a96f59135c62d.zip | |
Rename Chip to Arch and ChipArgs to ArchArgs
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40/arch_place.cc')
| -rw-r--r-- | ice40/arch_place.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 3205fb6e..d9210378 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -90,7 +90,7 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) bool isBelLocationValid(Design *design, BelId bel) { - const Chip &chip = design->chip; + const Arch &chip = design->chip; if (chip.getBelType(bel) == TYPE_ICESTORM_LC) { std::vector<const CellInfo *> cells; for (auto bel_other : chip.getBelsAtSameTile(bel)) { @@ -112,7 +112,7 @@ bool isBelLocationValid(Design *design, BelId bel) bool isValidBelForCell(Design *design, CellInfo *cell, BelId bel) { - const Chip &chip = design->chip; + const Arch &chip = design->chip; if (cell->type == "ICESTORM_LC") { assert(chip.getBelType(bel) == TYPE_ICESTORM_LC); |