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authorDavid Shah <davey1576@gmail.com>2018-06-13 11:08:20 +0200
committerDavid Shah <davey1576@gmail.com>2018-06-13 11:08:20 +0200
commit94eea289ae0fb4d262276d17c474ade3ef21634b (patch)
tree923e903f87f2d39cb4aa90867da150a0d1a64114 /ice40/cells.cc
parenta76f5c5678980c8b2e958252a68ba03676d63229 (diff)
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Simple IO buffer insertion, enable packer by default
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/cells.cc')
-rw-r--r--ice40/cells.cc36
1 files changed, 36 insertions, 0 deletions
diff --git a/ice40/cells.cc b/ice40/cells.cc
index ad728d2c..b038db68 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -60,6 +60,26 @@ CellInfo *create_ice_cell(Design *design, IdString type, IdString name)
add_port(new_cell, "LO", PORT_OUT);
add_port(new_cell, "O", PORT_OUT);
add_port(new_cell, "OUT", PORT_OUT);
+ } else if (type == "SB_IO") {
+ new_cell->params["PIN_TYPE"] = "0";
+ new_cell->params["PULLUP"] = "0";
+ new_cell->params["NEG_TRIGGER"] = "0";
+ new_cell->params["IOSTANDARD"] = "SB_LVCMOS";
+
+ add_port(new_cell, "PACKAGE_PIN", PORT_INOUT);
+
+ add_port(new_cell, "LATCH_INPUT_VALUE", PORT_IN);
+ add_port(new_cell, "CLOCK_ENABLE", PORT_IN);
+ add_port(new_cell, "INPUT_CLK", PORT_IN);
+ add_port(new_cell, "OUTPUT_CLK", PORT_IN);
+
+ add_port(new_cell, "OUTPUT_ENABLE", PORT_IN);
+ add_port(new_cell, "D_OUT_0", PORT_IN);
+ add_port(new_cell, "D_OUT_1", PORT_IN);
+
+ add_port(new_cell, "D_IN_0", PORT_OUT);
+ add_port(new_cell, "D_IN_1", PORT_OUT);
+
} else {
log_error("unable to create iCE40 cell of type %s", type.c_str());
}
@@ -128,4 +148,20 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
replace_port(dff, "Q", lc, "O");
}
+void nxio_to_sb(CellInfo *nxio, CellInfo *sbio)
+{
+ if (nxio->type == "$nextpnr_ibuf") {
+ sbio->params["PIN_TYPE"] = "1";
+ auto pu_attr = nxio->attrs.find("PULLUP");
+ if (pu_attr != nxio->attrs.end())
+ sbio->params["PULLUP"] = pu_attr->second;
+ replace_port(nxio, "O", sbio, "D_IN_0");
+ } else if (nxio->type == "$nextpnr_obuf") {
+ sbio->params["PIN_TYPE"] = "25";
+ replace_port(nxio, "I", sbio, "D_OUT_0");
+ } else {
+ assert(false);
+ }
+}
+
NEXTPNR_NAMESPACE_END