aboutsummaryrefslogtreecommitdiffstats
path: root/ice40/chip.h
diff options
context:
space:
mode:
authorDavid Shah <davey1576@gmail.com>2018-06-10 10:54:41 +0200
committerDavid Shah <davey1576@gmail.com>2018-06-10 10:54:55 +0200
commit48b72126c9f8f01bb22ab45f1bf0cc7c9ffb2c83 (patch)
tree84663dccee9d36811e4e872ebc99afb27bd76484 /ice40/chip.h
parent70f322ab449ce6786f1daacdc6c78df14a2ff5f5 (diff)
downloadnextpnr-48b72126c9f8f01bb22ab45f1bf0cc7c9ffb2c83.tar.gz
nextpnr-48b72126c9f8f01bb22ab45f1bf0cc7c9ffb2c83.tar.bz2
nextpnr-48b72126c9f8f01bb22ab45f1bf0cc7c9ffb2c83.zip
ice40: Add switch data to database
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ice40/chip.h')
-rw-r--r--ice40/chip.h48
1 files changed, 48 insertions, 0 deletions
diff --git a/ice40/chip.h b/ice40/chip.h
index a341bb14..97421e48 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -90,6 +90,8 @@ struct PipInfoPOD
int32_t src, dst;
float delay;
int8_t x, y;
+ int16_t switch_mask;
+ int32_t switch_index;
};
struct WireInfoPOD
@@ -105,6 +107,50 @@ struct WireInfoPOD
float x, y;
};
+enum TileType
+{
+ TILE_NONE,
+ TILE_LOGIC,
+ TILE_IO,
+ TILE_RAMB,
+ TILE_RAMT,
+};
+
+struct ConfigBitPOD
+{
+ int8_t row, col;
+};
+
+struct ConfigEntryPOD
+{
+ const char *name;
+ int num_bits;
+ ConfigBitPOD *bits;
+};
+
+struct TileBitsPOD
+{
+ int8_t width, height;
+ int num_config_entries;
+ ConfigEntryPOD *entries;
+};
+
+static const int max_switch_bits = 5;
+
+struct SwitchInfoPOD
+{
+ int8_t x, y;
+ int num_bits;
+ ConfigBitPOD cbits[max_switch_bits];
+};
+
+struct BitstreamInfoPOD
+{
+ int num_switches;
+ TileBitsPOD *tiles_nonrouting;
+ SwitchInfoPOD *switches;
+};
+
struct ChipInfoPOD
{
int width, height;
@@ -112,6 +158,8 @@ struct ChipInfoPOD
BelInfoPOD *bel_data;
WireInfoPOD *wire_data;
PipInfoPOD *pip_data;
+ TileType *tile_grid;
+ BitstreamInfoPOD *bits_info;
};
extern ChipInfoPOD chip_info_384;