aboutsummaryrefslogtreecommitdiffstats
path: root/ice40/chip.h
Commit message (Expand)AuthorAgeFilesLines
* Rename chip.h to arch.hClifford Wolf2018-06-181-757/+0
* Updates from clangformatClifford Wolf2018-06-181-2/+1
* Rename Chip to Arch and ChipArgs to ArchArgsClifford Wolf2018-06-181-6/+7
* Fix hash specialisation for BelType and warnings in place_sa.ccDavid Shah2018-06-181-0/+11
* Refactore ice40 chipdb to use a super-large C-string as output formatClifford Wolf2018-06-171-4/+4
* Updates from clangformatClifford Wolf2018-06-171-16/+13
* Move top-level ChipInfoPOD into ice40 chipdb blobClifford Wolf2018-06-171-41/+41
* Move PackageInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-3/+3
* Move TileType array to ice40 chipdb blobClifford Wolf2018-06-171-1/+1
* Move BitstreamInfoPOD to ice40 chipdb blobClifford Wolf2018-06-171-4/+4
* Move TileInfoPOD to chipdb blobClifford Wolf2018-06-171-2/+2
* Move SwitchInfoPOD to chipdb blobClifford Wolf2018-06-171-1/+1
* Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-171-10/+10
* Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-171-12/+17
* Progress with chipdb refactoringClifford Wolf2018-06-161-11/+15
* Progress with chipdb refactoringClifford Wolf2018-06-161-1/+1
* Progress with chipdb refactoringClifford Wolf2018-06-161-22/+23
* Merge remote-tracking branch 'origin/master' into chipdbngClifford Wolf2018-06-161-0/+1
|\
| * ice40: Only place IO at valid pinsDavid Shah2018-06-161-0/+1
* | Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-161-18/+40
|/
* Add route-ripup routing loopClifford Wolf2018-06-141-6/+12
* Refactor position/delay estimation APIClifford Wolf2018-06-141-9/+2
* Add hierarchy to bel/wire/pip namesClifford Wolf2018-06-131-10/+1
* Update chip Graphics APIClifford Wolf2018-06-131-1/+7
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-131-1/+19
|\
| * ice40: Add a PCF parserDavid Shah2018-06-131-0/+2
| * ice40: Add package selectionDavid Shah2018-06-131-0/+1
| * ice40: Add package pins to databaseDavid Shah2018-06-131-1/+16
* | Redesign PosInfo APIClifford Wolf2018-06-131-3/+11
|/
* Add fast IdString <-> PortPin conversionClifford Wolf2018-06-121-0/+1
* Add IdString APIClifford Wolf2018-06-121-3/+6
* Fix NEXTPNR_NAMESPACEClifford Wolf2018-06-121-6/+6
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-121-0/+2
|\
| * ice40: Adding a placement validity checkerDavid Shah2018-06-121-0/+2
* | Add nextpnr namespaceClifford Wolf2018-06-121-6/+14
|/
* Add "nextpnr.h"Clifford Wolf2018-06-111-2/+4
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-111-15/+15
* Add conflicting=false argument to bind gettersClifford Wolf2018-06-111-3/+4
* Pass design to gui, display chip nameMiodrag Milanovic2018-06-101-0/+2
* Improving 5k supportDavid Shah2018-06-101-0/+5
* Add support for iCE40 global buffers (currently only for 1k devices)Clifford Wolf2018-06-101-1/+2
* Fix ice40 pip/switch locked performance issueClifford Wolf2018-06-101-14/+7
* ice40: Add IO config to bitstreamDavid Shah2018-06-101-3/+12
* ice40: Lock out mutually exclusive pipsDavid Shah2018-06-101-2/+12
* ice40: Writing an empty ASC fileDavid Shah2018-06-101-0/+1
* ice40: Adding non-routing config bits to databaseDavid Shah2018-06-101-8/+8
* ice40: Add switch data to databaseDavid Shah2018-06-101-0/+48
* Getting rid of .nil() methods, compare with zero- and default-constructed obj...Clifford Wolf2018-06-091-32/+26
* Add very basic routerClifford Wolf2018-06-091-13/+93
* Applied clang-format to my own contributionsZipCPU2018-06-071-6/+11
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 15:00:27 +0000