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authorClifford Wolf <clifford@clifford.at>2018-08-19 18:44:25 +0200
committerGitHub <noreply@github.com>2018-08-19 18:44:25 +0200
commit634340cabb6ceaab5bfd75c48c86220e621fc1c9 (patch)
tree3f8204a00e13c994062377653ea586d660daa081 /ice40/chipdb.py
parent39e79db8547b0fb2e51267018add814a1c83e653 (diff)
parent801f63098348878d1dcd5e88735afeae014d7f22 (diff)
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Merge pull request #60 from YosysHQ/ice40ui
More iCE40 gfx
Diffstat (limited to 'ice40/chipdb.py')
-rw-r--r--ice40/chipdb.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index c33d736c..5b2f3e57 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -727,10 +727,6 @@ def add_pip(src, dst, flags=0):
pip_xy[(src, dst)] = (x, y, 0, len(switches) - 1, flags)
-# Add virtual padin wires
-for i in range(8):
- add_wire(0, 0, "padin_%d" % i)
-
def add_bel_input(bel, wire, port):
if wire not in wire_belports:
wire_belports[wire] = set()