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authorWilliam D. Jones <thor0505@comcast.net>2020-06-27 17:40:35 -0400
committergatecat <gatecat@ds0.me>2021-02-12 10:36:59 +0000
commit78880e1fdf1721a460c7e4e813f91f427106d3b7 (patch)
tree141a481404383e31cb52dc7d09c630552ad00904 /machxo2/examples/simple_timing.py
parent539651609cf82ab8e05cac636aee997e831b4d29 (diff)
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machxo2: Remove pybindings unneeded files from examples and update README.md and scripts accordingly. Delete resources directory.
Diffstat (limited to 'machxo2/examples/simple_timing.py')
-rw-r--r--machxo2/examples/simple_timing.py13
1 files changed, 0 insertions, 13 deletions
diff --git a/machxo2/examples/simple_timing.py b/machxo2/examples/simple_timing.py
deleted file mode 100644
index 1067b556..00000000
--- a/machxo2/examples/simple_timing.py
+++ /dev/null
@@ -1,13 +0,0 @@
-for cname, cell in ctx.cells:
- if cell.type != "GENERIC_SLICE":
- continue
- if cname in ("$PACKER_GND", "$PACKER_VCC"):
- continue
- K = int(cell.params["K"])
- ctx.addCellTimingClock(cell=cname, port="CLK")
- for i in range(K):
- ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK",
- setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0))
- ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2))
- for i in range(K):
- ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2))