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authorOlivier Galibert <galibert@pobox.com>2022-01-18 15:12:45 +0100
committerOlivier Galibert <galibert@pobox.com>2022-01-18 15:12:45 +0100
commitb5fc788153bd011a4476946af5ccebde05fd2ad2 (patch)
tree55768cd41e7d152c0213d21dfa5618aeca797333 /mistral/bitstream.cc
parent58a1b473b85ae8bc4312eed14af1829b93958341 (diff)
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Sync with the current state of mistral
Diffstat (limited to 'mistral/bitstream.cc')
-rw-r--r--mistral/bitstream.cc103
1 files changed, 4 insertions, 99 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index eed508b3..b432be03 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -29,108 +29,13 @@ struct MistralBitgen
Context *ctx;
CycloneV *cv;
- void init()
+ void options()
{
- ctx->init_base_bitstream();
- // Default options
- cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
- if (!ctx->setting<bool>("compress_rbf", false))
+ if (!ctx->setting<bool>("compress_rbf", false)) {
cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
- cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
- cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
- cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
- cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
- cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
- cv->opt_b_set(CycloneV::NCEO_DIS, true);
- cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
- cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
- if (!ctx->setting<bool>("compress_rbf", false))
cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
- else
+ } else
cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
- cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
- cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
- cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
- // Default inversion
- write_default_inv();
- }
-
- void write_default_inv()
- {
- // Some PNODEs are inverted by default. Set them up here.
- for (const auto &pn2r : cv->get_all_p2r()) {
- const auto &pn = pn2r.first;
- auto pt = CycloneV::pn2pt(pn);
- auto pi = CycloneV::pn2pi(pn);
-
- switch (CycloneV::pn2bt(pn)) {
- case CycloneV::HMC: {
- // HMC OE are inverted to set OE=0, i.e. unused pins floating
- // TODO: handle the case when we are using the HMC or HMC bypass
- std::string name(CycloneV::port_type_names[pt]);
- if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
- continue;
- cv->inv_set(pn2r.second, true);
- break;
- };
- // HPS IO - TODO: what about when we actually support the HPS primitives?
- case CycloneV::HPS_BOOT: {
- switch (pt) {
- case CycloneV::CSEL_EN:
- case CycloneV::BSEL_EN:
- case CycloneV::BOOT_FROM_FPGA_READY:
- case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
- cv->inv_set(pn2r.second, true);
- break;
- case CycloneV::CSEL:
- if (pi < 2)
- cv->inv_set(pn2r.second, true);
- break;
- case CycloneV::BSEL:
- if (pi < 3)
- cv->inv_set(pn2r.second, true);
- break;
- default:
- break;
- };
- break;
- };
- case CycloneV::HPS_CROSS_TRIGGER: {
- if (pt == CycloneV::CLK_EN)
- cv->inv_set(pn2r.second, true);
- break;
- };
- case CycloneV::HPS_TEST: {
- if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
- cv->inv_set(pn2r.second, true);
- break;
- };
- case CycloneV::GPIO: {
- // Ignore GPIO used by the design
- BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
- CycloneV::pn2bi(pn));
- if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
- continue;
- // Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
- // Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
- // GND, presumably for power/EMI reasons
- bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
- if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
- continue;
- if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
- continue;
- cv->inv_set(pn2r.second, true);
- break;
- };
- case CycloneV::FPLL: {
- if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
- cv->inv_set(pn2r.second, true);
- break;
- };
- default:
- break;
- }
- }
}
void write_dqs()
@@ -392,7 +297,7 @@ struct MistralBitgen
void run()
{
cv->clear();
- init();
+ options();
write_routing();
write_dqs();
write_cells();