diff options
| -rw-r--r-- | fpga_interchange/examples/tests/counter/counter.v | 8 | ||||
| -rw-r--r-- | fpga_interchange/examples/tests/counter/run_xilinx.tcl | 2 |
2 files changed, 6 insertions, 4 deletions
diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v index 00f52a20..4b3f343b 100644 --- a/fpga_interchange/examples/tests/counter/counter.v +++ b/fpga_interchange/examples/tests/counter/counter.v @@ -1,13 +1,15 @@ module top(input clk, input rst, output [7:4] io_led); -reg [31:0] counter = 32'b0; +localparam SIZE = 32; -assign io_led = counter >> 22; +reg [SIZE-1:0] counter = SIZE'b0; + +assign io_led = {counter[SIZE-1], counter[25:23]}; always @(posedge clk) begin if(rst) - counter <= 32'b0; + counter <= SIZE'b0; else counter <= counter + 1; end diff --git a/fpga_interchange/examples/tests/counter/run_xilinx.tcl b/fpga_interchange/examples/tests/counter/run_xilinx.tcl index ffea3b2e..c02cf933 100644 --- a/fpga_interchange/examples/tests/counter/run_xilinx.tcl +++ b/fpga_interchange/examples/tests/counter/run_xilinx.tcl @@ -2,7 +2,7 @@ yosys -import read_verilog $::env(SOURCES) -synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp +synth_xilinx -nolutram -nowidelut -nosrl -nodsp techmap -map $::env(TECHMAP) # opt_expr -undriven makes sure all nets are driven, if only by the $undef |