diff options
| -rw-r--r-- | ecp5/bitstream.cc | 2 | ||||
| -rw-r--r-- | ecp5/synth/cells.v | 2 | ||||
| -rw-r--r-- | ecp5/synth/simple_map.v | 6 | ||||
| -rw-r--r-- | ecp5/synth/ulx3s.v | 9 |
4 files changed, 9 insertions, 10 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 04bbc24f..f4f175bb 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -187,7 +187,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex for (const auto &tile : empty_chip.tiles) { std::string type = tile.second->info.type; if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") { - cc.tiles[type].add_enum("BANK.VCCIO", "3V3"); + cc.tiles[tile.first].add_enum("BANK.VCCIO", "3V3"); } } diff --git a/ecp5/synth/cells.v b/ecp5/synth/cells.v index 2435713a..d2c6d560 100644 --- a/ecp5/synth/cells.v +++ b/ecp5/synth/cells.v @@ -27,7 +27,7 @@ parameter CCU2_INJECT1_1 = "NO"; endmodule -(* blackbox *) +(* blackbox *) (* keep *) module TRELLIS_IO( inout B, input I, diff --git a/ecp5/synth/simple_map.v b/ecp5/synth/simple_map.v index 4a50fd01..550fa92c 100644 --- a/ecp5/synth/simple_map.v +++ b/ecp5/synth/simple_map.v @@ -25,7 +25,7 @@ module \$lut (A, Y); if (WIDTH == 1) begin TRELLIS_SLICE #( .MODE("LOGIC"), - .LUT0_INITVAL(LUT) + .LUT0_INITVAL({8{LUT[1:0]}}) ) _TECHMAP_REPLACE_ ( .A0(A[0]), .F0(Y) @@ -34,7 +34,7 @@ module \$lut (A, Y); if (WIDTH == 2) begin TRELLIS_SLICE #( .MODE("LOGIC"), - .LUT0_INITVAL(LUT) + .LUT0_INITVAL({4{LUT[3:0]}}) ) _TECHMAP_REPLACE_ ( .A0(A[0]), .B0(A[1]), @@ -44,7 +44,7 @@ module \$lut (A, Y); if (WIDTH == 3) begin TRELLIS_SLICE #( .MODE("LOGIC"), - .LUT0_INITVAL(LUT) + .LUT0_INITVAL({2{LUT[7:0]}}) ) _TECHMAP_REPLACE_ ( .A0(A[0]), .B0(A[1]), diff --git a/ecp5/synth/ulx3s.v b/ecp5/synth/ulx3s.v index 7f0786f5..25535e35 100644 --- a/ecp5/synth/ulx3s.v +++ b/ecp5/synth/ulx3s.v @@ -3,14 +3,13 @@ module top(input a_pin, output led_pin, output gpio0_pin); wire a; wire led; wire gpio0; - (* BEL="X90/Y65/PIOB" *) (* IO_TYPE="LVCMOS33" *) + (* BEL="X6/Y0/PIOB" *) (* IO_TYPE="LVCMOS33" *) TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a)); (* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led), .T(t)); + TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led)); (* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *) - TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0), .T(t)); + TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0)); assign led = !a; - wire t; - TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'h0000)) gnd (.F0(t)); + TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0)); endmodule |