diff options
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | ecp5/arch.cc | 25 | ||||
| -rw-r--r-- | ecp5/family.cmake | 41 | ||||
| -rw-r--r-- | ecp5/main.cc | 7 | ||||
| -rwxr-xr-x | ecp5/trellis_import.py | 6 |
5 files changed, 74 insertions, 6 deletions
@@ -2,6 +2,7 @@ /objs/ /nextpnr-generic* /nextpnr-ice40* +/nextpnr-ecp5* cmake-build-*/ Makefile cmake_install.cmake diff --git a/ecp5/arch.cc b/ecp5/arch.cc index fe10d415..a200e102 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -92,12 +92,20 @@ static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return void load_chipdb(); #endif +#define LFE5U_25F_ONLY + Arch::Arch(ArchArgs args) : args(args) { #if defined(_MSC_VER) load_chipdb(); #endif - +#ifdef LFE5U_25F_ONLY + if (args.type == ArchArgs::LFE5U_25F) { + chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_25k)); + } else { + log_error("Unsupported ECP5 chip type.\n"); + } +#else if (args.type == ArchArgs::LFE5U_25F) { chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_25k)); } else if (args.type == ArchArgs::LFE5U_45F) { @@ -107,6 +115,8 @@ Arch::Arch(ArchArgs args) : args(args) } else { log_error("Unsupported ECP5 chip type.\n"); } +#endif + } // ----------------------------------------------------------------------- @@ -302,4 +312,17 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const { return true; } bool Arch::isBelLocationValid(BelId bel) const { return true; } +// ----------------------------------------------------------------------- + + +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const +{ + return false; +} + +IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); } + +bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; } + + NEXTPNR_NAMESPACE_END diff --git a/ecp5/family.cmake b/ecp5/family.cmake index e69de29b..7f528886 100644 --- a/ecp5/family.cmake +++ b/ecp5/family.cmake @@ -0,0 +1,41 @@ + +set(devices 25k) + +set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/trellis_import.py) + +file(MAKE_DIRECTORY ecp5/chipdbs/) +add_library(ecp5_chipdb OBJECT ecp5/chipdbs/) +target_compile_definitions(ecp5_chipdb PRIVATE NEXTPNR_NAMESPACE=nextpnr_${family}) +target_include_directories(ecp5_chipdb PRIVATE ${family}/) +set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${TRELLIS_ROOT}/libtrellis:${TRELLIS_ROOT}/util/common") +if (MSVC) + target_sources(ecp5_chipdb PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/embed.cc) + set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resources/chipdb.rc PROPERTIES LANGUAGE RC) + foreach (dev ${devices}) + set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.bin) + set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/portpins.inc) + add_custom_command(OUTPUT ${DEV_CC_DB} + COMMAND ${ENV_CMD} python3 ${DB_PY} -b -p ${DEV_PORTS_INC} ${dev} ${DEV_CC_DB} + DEPENDS ${DB_PY} + ) + target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) + set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE) + foreach (target ${family_targets}) + target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb> ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/resource/chipdb.rc) + endforeach (target) + endforeach (dev) +else() + target_compile_options(ecp5_chipdb PRIVATE -g0 -O0 -w) + foreach (dev ${devices}) + set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/chipdbs/chipdb-${dev}.cc) + set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/portpins.inc) + add_custom_command(OUTPUT ${DEV_CC_DB} + COMMAND ${ENV_CMD} python3 ${DB_PY} -c -p ${DEV_PORTS_INC} ${dev} ${DEV_CC_DB} + DEPENDS ${DB_PY} + ) + target_sources(ecp5_chipdb PRIVATE ${DEV_CC_DB}) + foreach (target ${family_targets}) + target_sources(${target} PRIVATE $<TARGET_OBJECTS:ecp5_chipdb>) + endforeach (target) + endforeach (dev) +endif() diff --git a/ecp5/main.cc b/ecp5/main.cc index d025d8d4..55e835e3 100644 --- a/ecp5/main.cc +++ b/ecp5/main.cc @@ -89,8 +89,11 @@ int main(int argc, char *argv[]) "sha1 " GIT_COMMIT_HASH_STR ")\n"; return 1; } - - Context ctx(ArchArgs{}); + ArchArgs args; + args.type = ArchArgs::LFE5U_25F; + args.package = "CABGA381"; + args.speed = 6; + Context ctx(args); if (vm.count("verbose")) { ctx.verbose = true; diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index ff86098b..aabcffb1 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -602,7 +602,7 @@ def write_database(dev_name, endianness): bba.finalize() return bba -dev_names = {"LFE5U-25F": "25k", "LFE5U-45F": "45k", "LFE5U-85F": "85k"} +dev_names = {"25k": "LFE5U-25F", "45k": "LFE5U-45F", "85k": "LFE5U-85F"} def main(): global max_row, max_col @@ -623,7 +623,7 @@ def main(): portpins[line[1]] = idx print("Initialising chip...") - chip = pytrellis.Chip(args.device) + chip = pytrellis.Chip(dev_names[args.device]) print("Building routing graph...") rg = chip.get_routing_graph() max_row = chip.get_max_row() @@ -646,7 +646,7 @@ def main(): print(" At R{}C{}".format(y, x)) import_location(rg, x, y) print("{} unique location types".format(len(location_types))) - bba = write_database(dev_names[args.device], "le") + bba = write_database(args.device, "le") if args.c_file: |