diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 76 | ||||
| -rw-r--r-- | ecp5/arch.h | 2 | ||||
| -rw-r--r-- | ecp5/arch_place.cc | 5 | ||||
| -rw-r--r-- | ecp5/bitstream.cc | 13 | ||||
| -rw-r--r-- | ecp5/cells.cc | 2 | ||||
| -rw-r--r-- | ecp5/cells.h | 6 | ||||
| -rw-r--r-- | ecp5/gfx.cc | 45 | ||||
| -rw-r--r-- | ecp5/globals.cc | 22 | ||||
| -rw-r--r-- | ecp5/pack.cc | 41 |
9 files changed, 89 insertions, 123 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 0b763612..f031c904 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -557,8 +557,7 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const delay_t Arch::predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const { - if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin == id_FXA || dst_pin == id_FXB || - (src_pin == id_F && dst_pin == id_DI)) + if ((src_pin == id_FCO && dst_pin == id_FCI) || dst_pin.in(id_FXA, id_FXB) || (src_pin == id_F && dst_pin == id_DI)) return 0; auto driver_loc = getBelLocation(src_bel); auto sink_loc = getBelLocation(dst_bel); @@ -588,7 +587,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay if (net_info->driver.port == id_FCO && sink.port == id_FCI) { budget = 0; return true; - } else if (sink.port == id_FXA || sink.port == id_FXB) { + } else if (sink.port.in(id_FXA, id_FXB)) { budget = 0; return true; } else { @@ -819,8 +818,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort IdString tmg_type = has_carry ? (((cell->constr_z >> Arch::lc_idx_shift) % 2) ? id_TRELLIS_COMB_CARRY1 : id_TRELLIS_COMB_CARRY0) : id_TRELLIS_COMB; - if (fromPort == id_A || fromPort == id_B || fromPort == id_C || fromPort == id_D || fromPort == id_M || - fromPort == id_F1 || fromPort == id_FXA || fromPort == id_FXB || fromPort == id_FCI) + if (fromPort.in(id_A, id_B, id_C, id_D, id_M, id_F1, id_FXA, id_FXB, id_FCI)) return get_delay_from_tmg_db(tmg_type, fromPort, toPort, delay); else return false; @@ -842,7 +840,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort } return false; } else if (cell->type == id_DCSC) { - if ((fromPort == id_CLK0 || fromPort == id_CLK1) && toPort == id_DCSOUT) { + if ((fromPort.in(id_CLK0, id_CLK1)) && toPort == id_DCSOUT) { delay = DelayQuad(0); return true; } @@ -858,7 +856,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort return get_delay_from_tmg_db(cell->multInfo.timing_id, id(std::string("") + fn.front()), id_P, delay); } return false; - } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) { return false; } else { return false; @@ -872,18 +870,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in if (cell->type == id_TRELLIS_COMB) { if (port == id_WCK) return TMG_CLOCK_INPUT; - if (port == id_A || port == id_B || port == id_C || port == id_D || port == id_FCI || port == id_FXA || - port == id_FXB || port == id_F1) + if (port.in(id_A, id_B, id_C, id_D, id_FCI, id_FXA, id_FXB, id_F1)) return TMG_COMB_INPUT; if (port == id_F && disconnected(id_A) && disconnected(id_B) && disconnected(id_C) && disconnected(id_D) && disconnected(id_FCI)) return TMG_IGNORE; // LUT with no inputs is a constant - if (port == id_F || port == id_FCO || port == id_OFX) + if (port.in(id_F, id_FCO, id_OFX)) return TMG_COMB_OUTPUT; if (port == id_M) return TMG_COMB_INPUT; - if (port == id_WD || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 || - port == id_WRE) { + if (port.in(id_WD, id_WAD0, id_WAD1, id_WAD2, id_WAD3, id_WRE)) { clockInfoCount = 1; return TMG_REGISTER_INPUT; } @@ -892,7 +888,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED); if (port == id_CLK) return TMG_CLOCK_INPUT; - if (port == id_DI || (using_m && (port == id_M)) || port == id_CE || port == id_LSR) { + if (port == id_DI || (using_m && (port == id_M)) || port.in(id_CE, id_LSR)) { clockInfoCount = 1; return TMG_REGISTER_INPUT; } @@ -902,15 +898,13 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } return TMG_IGNORE; } else if (cell->type == id_TRELLIS_RAMW) { - if (port == id_A0 || port == id_A1 || port == id_B0 || port == id_B1 || port == id_C0 || port == id_C1 || - port == id_D0 || port == id_D1) + if (port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1)) return TMG_COMB_INPUT; - if (port == id_WDO0 || port == id_WDO1 || port == id_WDO2 || port == id_WDO3 || port == id_WADO0 || - port == id_WADO1 || port == id_WADO2 || port == id_WADO3) + if (port.in(id_WDO0, id_WDO1, id_WDO2, id_WDO3, id_WADO0, id_WADO1, id_WADO2, id_WADO3)) return TMG_COMB_OUTPUT; return TMG_IGNORE; } else if (cell->type == id_TRELLIS_IO) { - if (port == id_T || port == id_I) + if (port.in(id_T, id_I)) return TMG_ENDPOINT; if (port == id_O) return TMG_STARTPOINT; @@ -922,13 +916,13 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_COMB_OUTPUT; return TMG_IGNORE; } else if (cell->type == id_DCSC) { - if (port == id_CLK0 || port == id_CLK1) + if (port.in(id_CLK0, id_CLK1)) return TMG_COMB_INPUT; if (port == id_DCSOUT) return TMG_COMB_OUTPUT; return TMG_IGNORE; } else if (cell->type == id_DP16KD) { - if (port == id_CLKA || port == id_CLKB) + if (port.in(id_CLKA, id_CLKB)) return TMG_CLOCK_INPUT; std::string port_name = port.str(this); for (auto c : boost::adaptors::reverse(port_name)) { @@ -942,10 +936,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } NPNR_ASSERT_FALSE_STR("no timing type for RAM port '" + port.str(this) + "'"); } else if (cell->type == id_MULT18X18D) { - if (port == id_CLK0 || port == id_CLK1 || port == id_CLK2 || port == id_CLK3) + if (port.in(id_CLK0, id_CLK1, id_CLK2, id_CLK3)) return TMG_CLOCK_INPUT; - if (port == id_CE0 || port == id_CE1 || port == id_CE2 || port == id_CE3 || port == id_RST0 || - port == id_RST1 || port == id_RST2 || port == id_RST3 || port == id_SIGNEDA || port == id_SIGNEDB) { + if (port.in(id_CE0, id_CE1, id_CE2, id_CE3, id_RST0, id_RST1, id_RST2, id_RST3, id_SIGNEDA, id_SIGNEDB)) { if (cell->multInfo.is_clocked) { clockInfoCount = 1; return TMG_REGISTER_INPUT; @@ -977,9 +970,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_IGNORE; // FIXME } else if (cell->type == id_EHXPLLL) { return TMG_IGNORE; - } else if (cell->type == id_DCUA || cell->type == id_EXTREFB || cell->type == id_PCSCLKDIV) { - if (port == id_CH0_FF_TXI_CLK || port == id_CH0_FF_RXI_CLK || port == id_CH1_FF_TXI_CLK || - port == id_CH1_FF_RXI_CLK) + } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) { + if (port.in(id_CH0_FF_TXI_CLK, id_CH0_FF_RXI_CLK, id_CH1_FF_TXI_CLK, id_CH1_FF_RXI_CLK)) return TMG_CLOCK_INPUT; std::string prefix = port.str(this).substr(0, 9); if (prefix == "CH0_FF_TX" || prefix == "CH0_FF_RX" || prefix == "CH1_FF_TX" || prefix == "CH1_FF_RX") { @@ -987,18 +979,16 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; } return TMG_IGNORE; - } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { - if (port == id_CLK || port == id_ECLK) { + } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) { + if (port.in(id_CLK, id_ECLK)) { return TMG_CLOCK_INPUT; - } else if (port == id_IOLDO || port == id_IOLDOI || port == id_IOLDOD || port == id_IOLTO || port == id_PADDI || - port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) { + } else if (port.in(id_IOLDO, id_IOLDOI, id_IOLDOD, id_IOLTO, id_PADDI, id_DQSR90, id_DQSW, id_DQSW270)) { return TMG_IGNORE; } else { clockInfoCount = 1; return (cell->ports.at(port).type == PORT_OUT) ? TMG_REGISTER_OUTPUT : TMG_REGISTER_INPUT; } - } else if (cell->type == id_DTR || cell->type == id_USRMCLK || cell->type == id_SEDGA || cell->type == id_GSR || - cell->type == id_JTAGG) { + } else if (cell->type.in(id_DTR, id_USRMCLK, id_SEDGA, id_GSR, id_JTAGG)) { return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT; } else if (cell->type == id_OSCG) { if (port == id_OSC) @@ -1008,22 +998,22 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } else if (cell->type == id_CLKDIVF) { if (port == id_CLKI) return TMG_CLOCK_INPUT; - else if (port == id_RST || port == id_ALIGNWD) + else if (port.in(id_RST, id_ALIGNWD)) return TMG_ENDPOINT; else if (port == id_CDIVX) return TMG_GEN_CLOCK; else NPNR_ASSERT_FALSE("bad clkdiv port"); } else if (cell->type == id_DQSBUFM) { - if (port == id_READ0 || port == id_READ1) { + if (port.in(id_READ0, id_READ1)) { clockInfoCount = 1; return TMG_REGISTER_INPUT; } else if (port == id_DATAVALID) { clockInfoCount = 1; return TMG_REGISTER_OUTPUT; - } else if (port == id_SCLK || port == id_ECLK || port == id_DQSI) { + } else if (port.in(id_SCLK, id_ECLK, id_DQSI)) { return TMG_CLOCK_INPUT; - } else if (port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) { + } else if (port.in(id_DQSR90, id_DQSW, id_DQSW270)) { return TMG_GEN_CLOCK; } return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT; @@ -1054,8 +1044,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.hold = DelayPair(0); info.clockToQ = DelayQuad(0); if (cell->type == id_TRELLIS_COMB) { - if (port == id_WD || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 || port == id_WAD3 || - port == id_WRE) { + if (port.in(id_WD, id_WAD0, id_WAD1, id_WAD2, id_WAD3, id_WRE)) { if (port == id_WD) port = id_WD0; info.edge = (cell->combInfo.flags & ArchCellInfo::COMB_RAM_WCKINV) ? FALLING_EDGE : RISING_EDGE; @@ -1064,7 +1053,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port } } else if (cell->type == id_TRELLIS_FF) { bool using_m = (cell->ffInfo.flags & ArchCellInfo::FF_M_USED); - if (port == id_DI || port == id_CE || port == id_LSR || (using_m && port == id_M)) { + if (port.in(id_DI, id_CE, id_LSR) || (using_m && port == id_M)) { if (port == id_DI) port = id_DI0; if (port == id_M) @@ -1098,9 +1087,8 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port if (cell->ramInfo.is_pdp) { bool is_output = cell->ports.at(port).type == PORT_OUT; // In PDP mode, all read signals are in CLKB domain and write signals in CLKA domain - if (is_output || port == id_OCEB || port == id_CEB || port == id_ADB5 || port == id_ADB6 || - port == id_ADB7 || port == id_ADB8 || port == id_ADB9 || port == id_ADB10 || port == id_ADB11 || - port == id_ADB12 || port == id_ADB13) + if (is_output || port.in(id_OCEB, id_CEB, id_ADB5, id_ADB6, id_ADB7, id_ADB8, id_ADB9, id_ADB10, id_ADB11, + id_ADB12, id_ADB13)) info.clock_port = id_CLKB; else info.clock_port = id_CLKA; @@ -1133,7 +1121,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.setup = DelayPair(getDelayFromNS(1)); info.hold = DelayPair(getDelayFromNS(0)); } - } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) { + } else if (cell->type.in(id_IOLOGIC, id_SIOLOGIC)) { info.clock_port = id_CLK; info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { @@ -1147,7 +1135,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.edge = RISING_EDGE; if (port == id_DATAVALID) { info.clockToQ = DelayQuad(getDelayFromNS(0.2)); - } else if (port == id_READ0 || port == id_READ1) { + } else if (port.in(id_READ0, id_READ1)) { info.setup = DelayPair(getDelayFromNS(0.5)); info.hold = DelayPair(getDelayFromNS(-0.4)); } else { diff --git a/ecp5/arch.h b/ecp5/arch.h index 3d95fc9b..12f043b7 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -565,7 +565,7 @@ struct Arch : BaseArch<ArchRanges> void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell) { CellInfo *act_cell = (old_cell == nullptr) ? new_cell : old_cell; - if (act_cell->type == id_TRELLIS_FF || act_cell->type == id_TRELLIS_COMB || act_cell->type == id_TRELLIS_RAMW) { + if (act_cell->type.in(id_TRELLIS_FF, id_TRELLIS_COMB, id_TRELLIS_RAMW)) { LogicTileStatus *lts = tile_status.at(tile_index(bel)).lts; NPNR_ASSERT(lts != nullptr); int z = loc_info(bel)->bel_data[bel.index].z; diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc index afe9aca0..fed9c055 100644 --- a/ecp5/arch_place.cc +++ b/ecp5/arch_place.cc @@ -187,7 +187,7 @@ bool Arch::isBelLocationValid(BelId bel) const CellInfo *cell = getBoundBelCell(bel); if (cell == nullptr) { return true; - } else if (cell->type == id_DCUA || cell->type == id_EXTREFB || cell->type == id_PCSCLKDIV) { + } else if (cell->type.in(id_DCUA, id_EXTREFB, id_PCSCLKDIV)) { return args.type != ArchArgs::LFE5U_25F && args.type != ArchArgs::LFE5U_45F && args.type != ArchArgs::LFE5U_85F; } else { @@ -203,8 +203,7 @@ void Arch::setup_wire_locations() CellInfo *ci = cell.second.get(); if (ci->bel == BelId()) continue; - if (ci->type == id_MULT18X18D || ci->type == id_DCUA || ci->type == id_DDRDLL || ci->type == id_DQSBUFM || - ci->type == id_EHXPLLL) { + if (ci->type.in(id_MULT18X18D, id_DCUA, id_DDRDLL, id_DQSBUFM, id_EHXPLLL)) { for (auto &port : ci->ports) { if (port.second.net == nullptr) continue; diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 3c01fe71..37883bda 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -1110,25 +1110,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Tie signals as appropriate for (auto port : ci->ports) { - if (ci->ramInfo.is_pdp && (port.first == id_WEA || port.first == id_WEB || port.first == id_ADA4)) + if (ci->ramInfo.is_pdp && (port.first.in(id_WEA, id_WEB, id_ADA4))) continue; if (port.second.net == nullptr && port.second.type == PORT_IN) { - if (port.first == id_CLKA || port.first == id_CLKB || port.first == id_WEA || - port.first == id_WEB || port.first == id_RSTA || port.first == id_RSTB) { + if (port.first.in(id_CLKA, id_CLKB, id_WEA, id_WEB, id_RSTA, id_RSTB)) { // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB // If MUX doesn't exist, set to INV to emulate default 0 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true); if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX"))) ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV"); - } else if (port.first == id_CEA || port.first == id_CEB || port.first == id_OCEA || - port.first == id_OCEB) { + } else if (port.first.in(id_CEA, id_CEB, id_OCEA, id_OCEB)) { // CIB CE. Tie to "1" in CIB // If MUX doesn't exist, set to passthru to emulate default 1 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true); if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX"))) ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx); - } else if (port.first == id_CSA0 || port.first == id_CSA1 || port.first == id_CSA2 || - port.first == id_CSB0 || port.first == id_CSB1 || port.first == id_CSB2) { + } else if (port.first.in(id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) { // CIB CE. Tie to "1" in CIB. // If MUX doesn't exist, set to INV to emulate default 0 tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true); @@ -1392,7 +1389,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1)); cc.tilegroups.push_back(tg); - } else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) { + } else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC)) { Loc pio_loc = ctx->getBelLocation(ci->bel); pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4; std::string pic_tile = get_pic_tile(ctx, ctx->getBelByLocation(pio_loc)); diff --git a/ecp5/cells.cc b/ecp5/cells.cc index 99f672a6..23d4b855 100644 --- a/ecp5/cells.cc +++ b/ecp5/cells.cc @@ -133,7 +133,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str new_cell->addInput(id_CLKI); new_cell->addOutput(id_CLKO); new_cell->addInput(id_CE); - } else if (type == id_IOLOGIC || type == id_SIOLOGIC) { + } else if (type.in(id_IOLOGIC, id_SIOLOGIC)) { new_cell->params[id_MODE] = std::string("NONE"); new_cell->params[id_GSR] = std::string("DISABLED"); new_cell->params[id_CLKIMUX] = std::string("CLK"); diff --git a/ecp5/cells.h b/ecp5/cells.h index 185b19ce..c79bf8cd 100644 --- a/ecp5/cells.h +++ b/ecp5/cells.h @@ -47,15 +47,13 @@ inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->ty inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_IDDRX1F || cell->type == id_IDDRX2F || cell->type == id_IDDR71B || - cell->type == id_IDDRX2DQA || + return cell->type.in(id_IDDRX1F, id_IDDRX2F, id_IDDR71B, id_IDDRX2DQA) || (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) && (str_or_default(cell->attrs, id_ioff_dir, "") != "output")); } inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_ODDRX1F || cell->type == id_ODDRX2F || cell->type == id_ODDR71B || - cell->type == id_ODDRX2DQA || cell->type == id_ODDRX2DQSB || cell->type == id_OSHX2A || + return cell->type.in(id_ODDRX1F, id_ODDRX2F, id_ODDR71B, id_ODDRX2DQA, id_ODDRX2DQSB, id_OSHX2A) || (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) && (str_or_default(cell->attrs, id_ioff_dir, "") != "input")); } diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc index fe206de0..b1f3d4dd 100644 --- a/ecp5/gfx.cc +++ b/ecp5/gfx.cc @@ -84,8 +84,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int 3 * slice_pitch - 0.0007f; el.y2 = el.y1 + wire_distance * 5; g.push_back(el); - } else if (bel_type == id_TRELLIS_IO || bel_type == id_IOLOGIC || bel_type == id_SIOLOGIC || - bel_type == id_DQSBUFM) { + } else if (bel_type.in(id_TRELLIS_IO, id_IOLOGIC, id_SIOLOGIC, id_DQSBUFM)) { bool top_bottom = (y == 0 || y == (h - 1)); if (top_bottom) { el.x1 = x + io_cell_h_x1 + (z + 2) * io_cell_gap; @@ -115,7 +114,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int el.x2 = x + switchbox_x1 + (z)*0.025 + 0.020; el.y2 = y + 0.18; g.push_back(el); - } else if (bel_type == id_DP16KD || bel_type == id_MULT18X18D || bel_type == id_ALU54B) { + } else if (bel_type.in(id_DP16KD, id_MULT18X18D, id_ALU54B)) { el.x1 = x + slice_x1; el.x2 = x + slice_x2_wide; el.y1 = y + slice_y1 - 1 * slice_pitch; @@ -133,8 +132,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int el.y1 = y + slice_y2; el.y2 = y + 0.25; g.push_back(el); - } else if (bel_type == id_EXTREFB || bel_type == id_PCSCLKDIV || bel_type == id_DTR || bel_type == id_USRMCLK || - bel_type == id_SEDGA || bel_type == id_GSR || bel_type == id_JTAGG || bel_type == id_OSCG) { + } else if (bel_type.in(id_EXTREFB, id_PCSCLKDIV, id_DTR, id_USRMCLK, id_SEDGA, id_GSR, id_JTAGG, id_OSCG)) { el.x1 = x + slice_x1; el.x2 = x + slice_x2_wide; el.y1 = y + slice_y1 + (z)*slice_pitch; @@ -146,8 +144,7 @@ void gfxTileBel(std::vector<GraphicElement> &g, int x, int y, int z, int w, int el.y1 = y + dll_cell_y1; el.y2 = y + dll_cell_y2; g.push_back(el); - } else if (bel_type == id_DLLDELD || bel_type == id_CLKDIVF || bel_type == id_ECLKSYNCB || - bel_type == id_TRELLIS_ECLKBUF || bel_type == id_ECLKBRIDGECS) { + } else if (bel_type.in(id_DLLDELD, id_CLKDIVF, id_ECLKSYNCB, id_TRELLIS_ECLKBUF, id_ECLKBRIDGECS)) { el.x1 = x + 0.1 + z * 0.05; el.x2 = x + 0.14 + z * 0.05; el.y1 = y + 0.475; @@ -1455,15 +1452,13 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire dst_id - TILE_WIRE_JCE0); } - if ((src_type == id_WIRE_TYPE_H02 || src_type == id_WIRE_TYPE_V00 || src_type == id_WIRE_TYPE_V01 || - src_type == id_WIRE_TYPE_V02) && + if ((src_type.in(id_WIRE_TYPE_H02, id_WIRE_TYPE_V00, id_WIRE_TYPE_V01, id_WIRE_TYPE_V02)) && dst_type == id_WIRE_TYPE_NONE && ((dst_id >= TILE_WIRE_FCO && dst_id <= TILE_WIRE_FCI) || (dst_id >= TILE_WIRE_JCE0 && dst_id <= TILE_WIRE_JQ7))) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } - if ((dst_type == id_WIRE_TYPE_H02 || dst_type == id_WIRE_TYPE_V00 || dst_type == id_WIRE_TYPE_V01 || - dst_type == id_WIRE_TYPE_V02) && + if ((dst_type.in(id_WIRE_TYPE_H02, id_WIRE_TYPE_V00, id_WIRE_TYPE_V01, id_WIRE_TYPE_V02)) && src_type == id_WIRE_TYPE_NONE && ((src_id >= TILE_WIRE_FCO && src_id <= TILE_WIRE_FCI) || (src_id >= TILE_WIRE_JCE0 && src_id <= TILE_WIRE_JQ7))) { @@ -1480,33 +1475,27 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire } if (src_type == id_WIRE_TYPE_NONE && - (dst_type == id_WIRE_TYPE_PLL || dst_type == id_WIRE_TYPE_GSR || dst_type == id_WIRE_TYPE_JTAG || - dst_type == id_WIRE_TYPE_OSC || dst_type == id_WIRE_TYPE_SED || dst_type == id_WIRE_TYPE_DTR || - dst_type == id_WIRE_TYPE_EXTREF || dst_type == id_WIRE_TYPE_DCU || dst_type == id_WIRE_TYPE_PCSCLKDIV || - dst_type == id_WIRE_TYPE_DDRDLL || dst_type == id_WIRE_TYPE_CCLK || dst_type == id_WIRE_TYPE_DQS || - dst_type == id_WIRE_TYPE_IOLOGIC || dst_type == id_WIRE_TYPE_SIOLOGIC || dst_type == id_WIRE_TYPE_EBR || - dst_type == id_WIRE_TYPE_MULT18 || dst_type == id_WIRE_TYPE_ALU54) && + (dst_type.in(id_WIRE_TYPE_PLL, id_WIRE_TYPE_GSR, id_WIRE_TYPE_JTAG, id_WIRE_TYPE_OSC, id_WIRE_TYPE_SED, + id_WIRE_TYPE_DTR, id_WIRE_TYPE_EXTREF, id_WIRE_TYPE_DCU, id_WIRE_TYPE_PCSCLKDIV, + id_WIRE_TYPE_DDRDLL, id_WIRE_TYPE_CCLK, id_WIRE_TYPE_DQS, id_WIRE_TYPE_IOLOGIC, + id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_EBR, id_WIRE_TYPE_MULT18, id_WIRE_TYPE_ALU54)) && (src_id >= TILE_WIRE_JCE0 && src_id <= TILE_WIRE_JQ7)) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } if (dst_type == id_WIRE_TYPE_NONE && - (src_type == id_WIRE_TYPE_PLL || src_type == id_WIRE_TYPE_GSR || src_type == id_WIRE_TYPE_JTAG || - src_type == id_WIRE_TYPE_OSC || src_type == id_WIRE_TYPE_SED || src_type == id_WIRE_TYPE_DTR || - src_type == id_WIRE_TYPE_EXTREF || src_type == id_WIRE_TYPE_DCU || src_type == id_WIRE_TYPE_PCSCLKDIV || - src_type == id_WIRE_TYPE_DDRDLL || src_type == id_WIRE_TYPE_CCLK || src_type == id_WIRE_TYPE_DQS || - src_type == id_WIRE_TYPE_IOLOGIC || src_type == id_WIRE_TYPE_SIOLOGIC || src_type == id_WIRE_TYPE_EBR || - src_type == id_WIRE_TYPE_MULT18 || src_type == id_WIRE_TYPE_ALU54) && + (src_type.in(id_WIRE_TYPE_PLL, id_WIRE_TYPE_GSR, id_WIRE_TYPE_JTAG, id_WIRE_TYPE_OSC, id_WIRE_TYPE_SED, + id_WIRE_TYPE_DTR, id_WIRE_TYPE_EXTREF, id_WIRE_TYPE_DCU, id_WIRE_TYPE_PCSCLKDIV, + id_WIRE_TYPE_DDRDLL, id_WIRE_TYPE_CCLK, id_WIRE_TYPE_DQS, id_WIRE_TYPE_IOLOGIC, + id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_EBR, id_WIRE_TYPE_MULT18, id_WIRE_TYPE_ALU54)) && (dst_id >= TILE_WIRE_JCE0 && dst_id <= TILE_WIRE_JQ7)) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } - if (src_type == id_WIRE_TYPE_NONE && - (dst_type == id_WIRE_TYPE_IOLOGIC || dst_type == id_WIRE_TYPE_SIOLOGIC || dst_type == id_WIRE_TYPE_PIO) && + if (src_type == id_WIRE_TYPE_NONE && (dst_type.in(id_WIRE_TYPE_IOLOGIC, id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_PIO)) && (src_id >= TILE_WIRE_JDIA && src_id <= TILE_WIRE_ECLKD)) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } - if (dst_type == id_WIRE_TYPE_NONE && - (src_type == id_WIRE_TYPE_IOLOGIC || src_type == id_WIRE_TYPE_SIOLOGIC || src_type == id_WIRE_TYPE_PIO) && + if (dst_type == id_WIRE_TYPE_NONE && (src_type.in(id_WIRE_TYPE_IOLOGIC, id_WIRE_TYPE_SIOLOGIC, id_WIRE_TYPE_PIO)) && (dst_id >= TILE_WIRE_JDIA && dst_id <= TILE_WIRE_ECLKD)) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } @@ -1526,7 +1515,7 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, int w, int h, Wire (dst_id >= TILE_WIRE_CLK0 && dst_id <= TILE_WIRE_FCI))) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } - if ((dst_type == id_WIRE_TYPE_H01 || dst_type == id_WIRE_TYPE_V01) && src_type == id_WIRE_TYPE_G_HPBX) { + if ((dst_type.in(id_WIRE_TYPE_H01, id_WIRE_TYPE_V01)) && src_type == id_WIRE_TYPE_G_HPBX) { straightLine(g, el, x, y, w, h, src, src_type, src_id, dst, dst_type, dst_id); } } diff --git a/ecp5/globals.cc b/ecp5/globals.cc index 7123705a..6c7ffba0 100644 --- a/ecp5/globals.cc +++ b/ecp5/globals.cc @@ -57,10 +57,10 @@ class Ecp5GlobalRouter return true; if (user.cell->type == id_TRELLIS_COMB && user.port == id_WCK) return true; - if (user.cell->type == id_DCUA && (user.port == id_CH0_FF_RXI_CLK || user.port == id_CH1_FF_RXI_CLK || - user.port == id_CH0_FF_TXI_CLK || user.port == id_CH1_FF_TXI_CLK)) + if (user.cell->type == id_DCUA && + (user.port.in(id_CH0_FF_RXI_CLK, id_CH1_FF_RXI_CLK, id_CH0_FF_TXI_CLK, id_CH1_FF_TXI_CLK))) return true; - if ((user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC) && (user.port == id_CLK)) + if ((user.cell->type.in(id_IOLOGIC, id_SIOLOGIC)) && (user.port == id_CLK)) return true; return false; } @@ -88,7 +88,7 @@ class Ecp5GlobalRouter clockCount[ni->name]++; if (user.cell->type == id_DCUA) clockCount[ni->name] += 100; - if (user.cell->type == id_IOLOGIC || user.cell->type == id_SIOLOGIC) + if (user.cell->type.in(id_IOLOGIC, id_SIOLOGIC)) clockCount[ni->name] += 10; } } @@ -282,7 +282,7 @@ class Ecp5GlobalRouter bool route_onto_global(NetInfo *net, int network) { WireId glb_src; - NPNR_ASSERT(net->driver.cell->type == id_DCCA || net->driver.cell->type == id_DCSC); + NPNR_ASSERT(net->driver.cell->type.in(id_DCCA, id_DCSC)); glb_src = ctx->getNetinfoSourceWire(net); for (int quad = QUAD_UL; quad < QUAD_LR + 1; quad++) { WireId glb_dst = get_global_wire(GlobalQuadrant(quad), network); @@ -454,7 +454,7 @@ class Ecp5GlobalRouter { NetInfo *glbptr = nullptr; CellInfo *dccptr = nullptr; - if (net->driver.cell != nullptr && (net->driver.cell->type == id_DCCA || net->driver.cell->type == id_DCSC)) { + if (net->driver.cell != nullptr && (net->driver.cell->type.in(id_DCCA, id_DCSC))) { // Already have a DCC (such as clock gating) glbptr = net; dccptr = net->driver.cell; @@ -502,7 +502,7 @@ class Ecp5GlobalRouter int global_route_priority(const PortRef &load) { - if (load.port == id_WCK || load.port == id_WRE) + if (load.port.in(id_WCK, id_WRE)) return 90; return 99; } @@ -555,7 +555,7 @@ class Ecp5GlobalRouter dict<int, NetInfo *> clocks; for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); - if (ci->type == id_DCCA || ci->type == id_DCSC) { + if (ci->type.in(id_DCCA, id_DCSC)) { NetInfo *clock = ci->ports.at((ci->type == id_DCSC) ? id_DCSOUT : id_CLKO).net; NPNR_ASSERT(clock != nullptr); bool drives_fabric = false; @@ -591,7 +591,7 @@ class Ecp5GlobalRouter return global_route_priority(*a.first) < global_route_priority(*b.first); }); for (const auto &user : toroute) { - if (user.first->cell->type == id_DCSC && (user.first->port == id_CLK0 || user.first->port == id_CLK1)) { + if (user.first->cell->type == id_DCSC && (user.first->port.in(id_CLK0, id_CLK1))) { // Special case, skips most of the typical global network NetInfo *net = clocks.at(user.second); simple_router(net, ctx->getNetinfoSourceWire(net), ctx->getNetinfoSinkWire(net, *(user.first), 0)); @@ -606,9 +606,9 @@ class Ecp5GlobalRouter // Try and use dedicated paths if possible for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); - if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF || ci->type == id_ECLKBRIDGECS) { + if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF, id_ECLKBRIDGECS)) { std::vector<IdString> pins; - if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) { + if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) { pins.push_back(id_ECLKI); } else { pins.push_back(id_CLK0); diff --git a/ecp5/pack.cc b/ecp5/pack.cc index 4cd33dee..4c8ceee8 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -266,11 +266,10 @@ class Ecp5Packer if (port.cell == nullptr) return false; if (port.cell->type == id_DCUA) { - return port.port == id_CH0_HDINP || port.port == id_CH0_HDINN || port.port == id_CH0_HDOUTP || - port.port == id_CH0_HDOUTN || port.port == id_CH1_HDINP || port.port == id_CH1_HDINN || - port.port == id_CH1_HDOUTP || port.port == id_CH1_HDOUTN; + return port.port.in(id_CH0_HDINP, id_CH0_HDINN, id_CH0_HDOUTP, id_CH0_HDOUTN, id_CH1_HDINP, id_CH1_HDINN, + id_CH1_HDOUTP, id_CH1_HDOUTN); } else if (port.cell->type == id_EXTREFB) { - return port.port == id_REFCLKP || port.port == id_REFCLKN; + return port.port.in(id_REFCLKP, id_REFCLKN); } else { return false; } @@ -905,13 +904,11 @@ class Ecp5Packer uc->params[id_CEMUX] = std::string(constval ? "1" : "0"); uc->ports[user.port].net = nullptr; } else if (is_carry(ctx, uc)) { - if (constval && - (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 || - user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) { + if (constval && (user.port.in(id_A0, id_A1, id_B0, id_B1, id_C0, id_C1, id_D0, id_D1))) { // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high) uc->ports[user.port].net = nullptr; } else if (!constval) { - if (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1) { + if (user.port.in(id_A0, id_A1, id_B0, id_B1)) { // These inputs can be switched to tie-high without consequence set_ccu2c_input_constant(uc, user.port, constval); } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) { @@ -940,10 +937,8 @@ class Ecp5Packer (constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "INV"))) { uc->ports[user.port].net = nullptr; } else if (uc->type == id_DP16KD) { - if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB || - user.port == id_WEA || user.port == id_WEB || user.port == id_CEA || user.port == id_CEB || - user.port == id_OCEA || user.port == id_OCEB || user.port == id_CSA0 || user.port == id_CSA1 || - user.port == id_CSA2 || user.port == id_CSB0 || user.port == id_CSB1 || user.port == id_CSB2) { + if (user.port.in(id_CLKA, id_CLKB, id_RSTA, id_RSTB, id_WEA, id_WEB, id_CEA, id_CEB, id_OCEA, + id_OCEB, id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) { // Connect to CIB CLK, LSR or CE. Default state is 1 uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? user.port.str(ctx) : "INV"; } else { @@ -951,7 +946,7 @@ class Ecp5Packer uc->params[ctx->id(user.port.str(ctx) + "MUX")] = std::string(constval ? "1" : "0"); } uc->ports[user.port].net = nullptr; - } else if (uc->type == id_ALU54B || uc->type == id_MULT18X18D) { + } else if (uc->type.in(id_ALU54B, id_MULT18X18D)) { if (user.port.str(ctx).substr(0, 3) == "CLK" || user.port.str(ctx).substr(0, 2) == "CE" || user.port.str(ctx).substr(0, 3) == "RST" || user.port.str(ctx).substr(0, 3) == "SRO" || user.port.str(ctx).substr(0, 3) == "SRI" || user.port.str(ctx).substr(0, 2) == "RO" || @@ -1350,7 +1345,7 @@ class Ecp5Packer if (net == nullptr || net->driver.cell == nullptr) continue; IdString ct = net->driver.cell->type; - if (ct == id_GND || ct == id_VCC) { + if (ct.in(id_GND, id_VCC)) { ci->disconnectPort(ndport); ci->ports.erase(ndport); } @@ -1442,7 +1437,7 @@ class Ecp5Packer ci->renamePort(id_USRMCLKI, id_PADDO); ci->renamePort(id_USRMCLKTS, id_PADDT); ci->renamePort(id_USRMCLKO, id_PADDI); - } else if (ci->type == id_GSR || ci->type == id_SGSR) { + } else if (ci->type.in(id_GSR, id_SGSR)) { ci->params[id_MODE] = std::string("ACTIVE_LOW"); ci->params[id_SYNCMODE] = ci->type == id_SGSR ? std::string("SYNC") : std::string("ASYNC"); ci->type = id_GSR; @@ -1894,7 +1889,7 @@ class Ecp5Packer for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); - if (ci->type == id_DELAYF || ci->type == id_DELAYG) { + if (ci->type.in(id_DELAYF, id_DELAYG)) { CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(id_A).net, is_trellis_io, id_O); CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(id_Z).net, is_trellis_io, id_I, true); CellInfo *iol = nullptr; @@ -2021,7 +2016,7 @@ class Ecp5Packer ci->movePortTo(id_D1, iol, id_TXDATA1); iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED"); packed_cells.insert(cell.first); - } else if (ci->type == id_ODDRX2F || ci->type == id_ODDR71B) { + } else if (ci->type.in(id_ODDRX2F, id_ODDR71B)) { CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true); if (pio == nullptr) log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx), @@ -2061,7 +2056,7 @@ class Ecp5Packer iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED"); pio->params[id_DATAMUX_ODDR] = std::string("IOLDO"); packed_cells.insert(cell.first); - } else if (ci->type == id_IDDRX2F || ci->type == id_IDDR71B) { + } else if (ci->type.in(id_IDDRX2F, id_IDDR71B)) { CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O); if (pio == nullptr || ci->ports.at(id_D).net->users.entries() > 1) log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx), @@ -2121,7 +2116,7 @@ class Ecp5Packer iol->params[ctx->id("MODDRX.MODE")] = std::string("MOSHX2"); pio->params[id_DATAMUX_MDDR] = std::string("IOLDO"); packed_cells.insert(cell.first); - } else if (ci->type == id_ODDRX2DQA || ci->type == id_ODDRX2DQSB) { + } else if (ci->type.in(id_ODDRX2DQA, id_ODDRX2DQSB)) { CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true); if (pio == nullptr) log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx), @@ -2183,7 +2178,7 @@ class Ecp5Packer process_dqs_port(ci, pio, iol, id_WRPNTR1); process_dqs_port(ci, pio, iol, id_WRPNTR0); packed_cells.insert(cell.first); - } else if (ci->type == id_TSHX2DQA || ci->type == id_TSHX2DQSA) { + } else if (ci->type.in(id_TSHX2DQA, id_TSHX2DQSA)) { CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_T, true); if (pio == nullptr) log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx), @@ -2388,7 +2383,7 @@ class Ecp5Packer // Promote/route edge clocks for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); - if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) { + if (ci->type.in(id_IOLOGIC, id_DQSBUFM)) { if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr) continue; BelId bel = ctx->getBelByNameStr(str_or_default(ci->attrs, id_BEL)); @@ -2669,7 +2664,7 @@ class Ecp5Packer pool<IdString> changed_cells; for (auto net : changed_nets) { for (auto &user : ctx->nets.at(net)->users) - if (user.port == id_CLKI || user.port == id_ECLKI || user.port == id_CLK0 || user.port == id_CLK1) + if (user.port.in(id_CLKI, id_ECLKI, id_CLK0, id_CLK1)) changed_cells.insert(user.cell->name); auto &drv = ctx->nets.at(net)->driver; if (iter == 1 && drv.cell != nullptr && drv.port == id_OSC) @@ -2688,7 +2683,7 @@ class Ecp5Packer else log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx)); copy_constraint(ci, id_CLKI, id_CDIVX, ratio); - } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) { + } else if (ci->type.in(id_ECLKSYNCB, id_TRELLIS_ECLKBUF)) { copy_constraint(ci, id_ECLKI, id_ECLKO, 1); } else if (ci->type == id_ECLKBRIDGECS) { copy_constraint(ci, id_CLK0, id_ECSOUT, 1); |