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-rw-r--r--fpga_interchange/arch.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 6a7c4fe1..3ce9f79e 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -907,7 +907,7 @@ static void prepare_sites_for_routing(Context *ctx)
// We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for
// Nexus they are the same) so add a prefix to the bel pin name to disambiguate it
- IdString cell_pin = ctx->id(stringf("%s_PHYS", ctx->nameOf(bel_pin)));
+ IdString cell_pin = ctx->idf("%s_PHYS", ctx->nameOf(bel_pin));
PortInfo port_info;
port_info.name = cell_pin;