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-rw-r--r--fpga_interchange/examples/wire/Makefile8
1 files changed, 8 insertions, 0 deletions
diff --git a/fpga_interchange/examples/wire/Makefile b/fpga_interchange/examples/wire/Makefile
new file mode 100644
index 00000000..49194f53
--- /dev/null
+++ b/fpga_interchange/examples/wire/Makefile
@@ -0,0 +1,8 @@
+DESIGN := wire
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/wire.json: wire.v | build
+ yosys -c run.tcl