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path: root/fpga_interchange/examples/wire/Makefile
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DESIGN := wire
DESIGN_TOP := top
PACKAGE := csg324

include ../template.mk

build/wire.json: wire.v | build
	yosys -c run.tcl
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 21:54:47 +0000