aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/site_router.cc
diff options
context:
space:
mode:
Diffstat (limited to 'fpga_interchange/site_router.cc')
-rw-r--r--fpga_interchange/site_router.cc3
1 files changed, 1 insertions, 2 deletions
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index f4d65958..69bd366f 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -59,8 +59,7 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
BelId bel = cell->bel;
for (const auto &pin_pair : cell->cell_bel_pins) {
if (!cell->ports.count(pin_pair.first))
- log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
- pin_pair.first.c_str(ctx));
+ continue;
const PortInfo &port = cell->ports.at(pin_pair.first);
NPNR_ASSERT(port.net != nullptr);