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* Add stub cluster API impl for remaining archesgatecat2021-05-067-2/+34
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Use new cluster APIgatecat2021-05-063-13/+17
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* base_arch: Fix typo in getClusterPlacementgatecat2021-05-061-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use new cluster APIgatecat2021-05-063-20/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update placers to use new cluster APIsgatecat2021-05-0610-346/+151
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add default base implementation of cluster APIgatecat2021-05-066-7/+104
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add BaseClusterInfo for base implementationgatecat2021-05-061-0/+44
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* arch_api: Outline of new cluster APIgatecat2021-05-064-14/+43
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #692 from davidcorrigan714/patch-1gatecat2021-05-011-2/+2
|\ | | | | Fix variable name in bits.h for MSVC builds
| * Update bits.hDavid Corrigan2021-04-301-2/+2
|/ | | Fixed the variable name for windows MSVC builds.
* clangformatgatecat2021-04-301-40/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #664 from YosysHQ/gatecat/nexus-countergatecat2021-04-308-3/+61
|\ | | | | interchange/nexus: Add counter example
| * interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #690 from YosysHQ/gatecat/interchange-wire-typesgatecat2021-04-305-4/+39
|\ | | | | interchange: Add wire types
| * interchange: Bump versionsgatecat2021-04-301-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Implement getWireTypegatecat2021-04-303-1/+20
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #689 from adamgreig/ecp5-alugatecat2021-04-293-1/+140
|\ | | | | ECP5 ALU54B placement support
| * Only set CIBOUT_BYP on MULTs that are not feeding an ALU.Adam Greig2021-04-291-1/+1
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| * Add check_alu to Ecp5PackerAdam Greig2021-04-291-15/+123
| | | | | | | | | | | | | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible.
| * Add relative constraints to position MULT18X18D near connected ALU54B.Adam Greig2021-04-292-0/+29
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| * Add ALU54B.REG_OPCODEOP1_1_CLK parameter supportAdam Greig2021-04-291-0/+2
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* Merge pull request #685 from YosysHQ/gatecat/nexus-routinggatecat2021-04-251-4/+1
|\ | | | | nexus: Enable placeAllAtOnce
| * nexus: Enable placeAllAtOncegatecat2021-04-251-4/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
|\ | | | | interchange: allow LOC keyword in XDC files
| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
| | | | | | | | Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
* | Merge pull request #682 from YosysHQ/gatecat/default-cellpinsgatecat2021-04-206-8/+81
|\ \ | | | | | | interchange: Handle missing/disconnected cell pins
| * | interchange: Bump versionsgatecat2021-04-202-1/+1
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-152-0/+8
|\ \ | | | | | | Add Python bindings for placement tests
| * | Add Python bindings for placement testsgatecat2021-04-152-0/+8
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #680 from YosysHQ/gatecat/fix-utilgatecat2021-04-151-2/+2
|\ \ \ | |/ / |/| | Fix utilisation report when bel buckets are used
| * | Fix utilisation report when bel buckets are usedgatecat2021-04-151-2/+2
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1421-71/+136
|\ \ | | | | | | interchange: add FASM generation target and clean-up tests
| * | gh-actions: increase python-fpga-interchange tag versionAlessandro Comodi2021-04-141-1/+1
| | | | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
| |/ | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #679 from YosysHQ/gatecat/disable-abslgatecat2021-04-1411-63/+54
|\ \ | |/ |/| Hash table changes
| * ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Hash table refactoringgatecat2021-04-1410-62/+53
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #677 from YosysHQ/gatecat/ppip-no-inputgatecat2021-04-131-14/+35
|\ | | | | interchange: Allow pseudo-cells with no input pins
| * interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
| | | | | | | | | | | | | | These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch, which will probably be required for UltraScale too. Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #676 from YosysHQ/gatecat/fix-sta-crashgatecat2021-04-132-58/+73
|\ \ | |/ |/| timing: Fix domain init when loops are present
| * timing: Fix domain init when loops are presentgatecat2021-04-132-58/+73
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #674 from adamgreig/heap-spreader-fixgatecat2021-04-121-0/+4
|\ | | | | HeAP: Skip high-strength cells in both cell loops
| * HeAP: Skip high-strength cells in both cell loops.Adam Greig2021-04-121-0/+4
| | | | | | | | | | | | Previously only the first loop skipped cells with high belStrength, but they can't be processed by the second loop either, so skip them there too.
* | Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-refgatecat2021-04-121-14/+18
|\ \ | |/ |/| fast_bels: Don't return pointer that might become invalid
| * fast_bels: Don't return pointer that might become invalidgatecat2021-04-121-14/+18
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-04-128-133/+134
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vccgatecat2021-04-091-6/+10
|\ | | | | interchange: Disambiguate cell and bel pins when creating Vcc ties
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