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| | * Experimenting with more unplacingDavid Shah2018-06-161-6/+11
| | * Adding randomness and changes metrics to placerDavid Shah2018-06-161-9/+25
| | * Updating placerDavid Shah2018-06-161-7/+35
| | * Update basic placer to use new APIDavid Shah2018-06-161-4/+10
| | * Another heuristic experimentDavid Shah2018-06-161-77/+18
| | * Playing about with placement heuristicsDavid Shah2018-06-161-5/+19
| | * experiment: Simple heuristic-based placerDavid Shah2018-06-167-9/+139
* | | Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-167-60/+93
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* | Fix router for routing to the same dest wire twiceClifford Wolf2018-06-151-21/+16
* | Create all without ui file, enables more controlMiodrag Milanovic2018-06-154-173/+93
* | Propagate signalsMiodrag Milanovic2018-06-154-2/+13
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* ice40: Another arch_place fixDavid Shah2018-06-141-1/+1
* ice40: General fixesDavid Shah2018-06-142-11/+21
* ice40: Read cells in arachne placement scriptDavid Shah2018-06-141-1/+1
* ice40: Importer for placed ice40 designs from arachneDavid Shah2018-06-143-0/+35
* Added back some size limits for UIMiodrag Milanovic2018-06-143-4/+9
* Split design widget on sideMiodrag Milanovic2018-06-146-258/+289
* separate clearPropertiesMiodrag Milanovic2018-06-142-4/+12
* CleanupMiodrag Milanovic2018-06-145-7/+6
* Split to classesMiodrag Milanovic2018-06-147-136/+169
* Split per widgetsMiodrag Milanovic2018-06-142-360/+414
* Add output of estimated total wire delay to router (as metric for placement q...Clifford Wolf2018-06-141-0/+49
* Increase ripup penalties over timeClifford Wolf2018-06-141-2/+8
* Add route-ripup routing loopClifford Wolf2018-06-143-38/+188
* Refactor position/delay estimation APIClifford Wolf2018-06-146-87/+37
* python: Clear SIGINT handler after Python loadsDavid Shah2018-06-141-0/+2
* Drastically reduce number of linker symbols in chipdbClifford Wolf2018-06-131-18/+40
* Cleanup and preps for further ui workMiodrag Milanovic2018-06-133-62/+48
* Make custom types for elements in tree viewMiodrag Milanovic2018-06-132-177/+145
* Improve router error reportingClifford Wolf2018-06-131-4/+15
* ice40: Rename ICESTORM_RAM pinsDavid Shah2018-06-132-3/+56
* Improve router error messagesClifford Wolf2018-06-131-5/+13
* Add support for CellInfo->pins in routerClifford Wolf2018-06-132-5/+17
* Add picorv32_top module with fewer IO pinsClifford Wolf2018-06-132-1/+32
* frontend/json: Fix bus portsDavid Shah2018-06-131-1/+1
* Fix router error handling for unplaced cellsClifford Wolf2018-06-131-2/+5
* Add missing iCE40 global buffer belsClifford Wolf2018-06-131-0/+18
* Add test PicoRV32 build scriptClifford Wolf2018-06-132-0/+7
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-132-3/+38
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| * ice40: Pack RAMsDavid Shah2018-06-133-8/+46
* | Add A*-like optimizations to routerClifford Wolf2018-06-138-31/+97
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* tests: Fix ice40 testsDavid Shah2018-06-136-0/+6
* ice40: Promote one clock to a global bufferDavid Shah2018-06-133-1/+61
* Add hierarchy to bel/wire/pip namesClifford Wolf2018-06-134-19/+31
* Fixing implementation of constantsDavid Shah2018-06-134-9/+55
* Update READMEDavid Shah2018-06-131-4/+3
* cmake: Fixing the installerDavid Shah2018-06-132-1/+3
* ice40: Update examples to use packer/pcfDavid Shah2018-06-1310-398/+37
* Update chip Graphics APIClifford Wolf2018-06-134-23/+35
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-1328-351/+1078
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