| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #702 from YosysHQ/gatecat/interchange-fix-bb | gatecat | 2021-05-11 | 2 | -3/+3 |
| |\ | | | | | interchange: Fix bounding box computation | ||||
| | * | router2: Fix a typo | gatecat | 2021-05-11 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Fix bounding box computation | gatecat | 2021-05-11 | 1 | -2/+2 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #701 from YosysHQ/gatecat/finer-debug | gatecat | 2021-05-11 | 1 | -0/+11 |
| |\ | | | | | command: Allow debug output for just placer or router | ||||
| | * | command: Allow debug output for just placer or router | gatecat | 2021-05-11 | 1 | -0/+11 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #695 from acomodi/fix-illegal-site-thru | gatecat | 2021-05-10 | 2 | -2/+25 |
| |\ | | | | | interchange: fix site-thru pip legality | ||||
| | * | interchange: site router: fix log messages | Alessandro Comodi | 2021-05-10 | 1 | -3/+3 |
| | | | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| | * | interchange: site router: fix illegal site thru paths | Alessandro Comodi | 2021-05-10 | 2 | -0/+23 |
| |/ | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | Merge pull request #694 from YosysHQ/gatecat/interchange-glbroute | gatecat | 2021-05-07 | 5 | -2/+337 |
| |\ | | | | | interchange: Initial global routing implementation | ||||
| | * | interchange: Bump version | gatecat | 2021-05-07 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Adding a basic global buffer placer | gatecat | 2021-05-07 | 3 | -32/+132 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Initial global routing implementation | gatecat | 2021-05-07 | 3 | -0/+222 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Add more global cell info | gatecat | 2021-05-07 | 1 | -1/+14 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #697 from YosysHQ/gatecat/router2-dynamic-bb-expand | gatecat | 2021-05-06 | 1 | -23/+61 |
| |\ | | | | | router2: Dynamicly expand bounding box based on congestion | ||||
| | * | router2: Reserve wires in more complex cases | gatecat | 2021-05-06 | 1 | -13/+39 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | router2: Dynamicly expand bounding box based on congestion | gatecat | 2021-05-06 | 1 | -10/+22 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Revert "nexus: Enable placeAllAtOnce" | gatecat | 2021-05-06 | 1 | -1/+4 |
| | | | | | This reverts commit 0abe425675ae0cc550194171f1f15ec4058a05d6. | ||||
| * | Merge pull request #688 from YosysHQ/gatecat/new-cluster-api | gatecat | 2021-05-06 | 26 | -391/+411 |
| |\ | | | | | New cluster API | ||||
| | * | Add stub cluster API impl for remaining arches | gatecat | 2021-05-06 | 7 | -2/+34 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | nexus: Use new cluster API | gatecat | 2021-05-06 | 3 | -13/+17 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | base_arch: Fix typo in getClusterPlacement | gatecat | 2021-05-06 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | ecp5: Use new cluster API | gatecat | 2021-05-06 | 3 | -20/+29 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | Update placers to use new cluster APIs | gatecat | 2021-05-06 | 10 | -346/+151 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | Add default base implementation of cluster API | gatecat | 2021-05-06 | 6 | -7/+104 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | Add BaseClusterInfo for base implementation | gatecat | 2021-05-06 | 1 | -0/+44 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | arch_api: Outline of new cluster API | gatecat | 2021-05-06 | 4 | -14/+43 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #692 from davidcorrigan714/patch-1 | gatecat | 2021-05-01 | 1 | -2/+2 |
| |\ | | | | | Fix variable name in bits.h for MSVC builds | ||||
| | * | Update bits.h | David Corrigan | 2021-04-30 | 1 | -2/+2 |
| |/ | | | Fixed the variable name for windows MSVC builds. | ||||
| * | clangformat | gatecat | 2021-04-30 | 1 | -40/+30 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #664 from YosysHQ/gatecat/nexus-counter | gatecat | 2021-04-30 | 8 | -3/+61 |
| |\ | | | | | interchange/nexus: Add counter example | ||||
| | * | interchange/nexus: Add counter example | gatecat | 2021-04-30 | 8 | -3/+61 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #690 from YosysHQ/gatecat/interchange-wire-types | gatecat | 2021-04-30 | 5 | -4/+39 |
| |\ | | | | | interchange: Add wire types | ||||
| | * | interchange: Bump versions | gatecat | 2021-04-30 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Implement getWireType | gatecat | 2021-04-30 | 3 | -1/+20 |
| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | interchange: Add wire types to chipdb | gatecat | 2021-04-30 | 1 | -1/+17 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #689 from adamgreig/ecp5-alu | gatecat | 2021-04-29 | 3 | -1/+140 |
| |\ | | | | | ECP5 ALU54B placement support | ||||
| | * | Only set CIBOUT_BYP on MULTs that are not feeding an ALU. | Adam Greig | 2021-04-29 | 1 | -1/+1 |
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| | * | Add check_alu to Ecp5Packer | Adam Greig | 2021-04-29 | 1 | -15/+123 |
| | | | | | | | | | | | | | | | | | | | | | | | Checks that every ALU54B is correctly connected to two MULT18X18Ds: * SIGNEDIA and SIGNEDIB connected to SIGNEDP * MA and MB connected to P * A and B connected to {ROA, ROB} Diamond enforces these requirements; the connections are fixed in any event so no other connection is possible. | ||||
| | * | Add relative constraints to position MULT18X18D near connected ALU54B. | Adam Greig | 2021-04-29 | 2 | -0/+29 |
| | | | |||||
| | * | Add ALU54B.REG_OPCODEOP1_1_CLK parameter support | Adam Greig | 2021-04-29 | 1 | -0/+2 |
| |/ | |||||
| * | Merge pull request #685 from YosysHQ/gatecat/nexus-routing | gatecat | 2021-04-25 | 1 | -4/+1 |
| |\ | | | | | nexus: Enable placeAllAtOnce | ||||
| | * | nexus: Enable placeAllAtOnce | gatecat | 2021-04-25 | 1 | -4/+1 |
| |/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Merge pull request #683 from antmicro/interchange-allow-loc-keyword | gatecat | 2021-04-20 | 1 | -2/+4 |
| |\ | | | | | interchange: allow LOC keyword in XDC files | ||||
| | * | interchange: allow LOC keyword in XDC files | Jan Kowalewski | 2021-04-20 | 1 | -2/+4 |
| | | | | | | | | | Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com> | ||||
| * | | Merge pull request #682 from YosysHQ/gatecat/default-cellpins | gatecat | 2021-04-20 | 6 | -8/+81 |
| |\ \ | | | | | | | interchange: Handle missing/disconnected cell pins | ||||
| | * | | interchange: Bump versions | gatecat | 2021-04-20 | 2 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | | interchange: Handle disconnected/missing cell pins | gatecat | 2021-04-19 | 3 | -6/+56 |
| | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| | * | | interchange: Add default cell connections to chipdb | gatecat | 2021-04-19 | 1 | -1/+24 |
| |/ / | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | | Merge pull request #681 from YosysHQ/gatecat/more-pybindings | gatecat | 2021-04-15 | 2 | -0/+8 |
| |\ \ | | | | | | | Add Python bindings for placement tests | ||||
| | * | | Add Python bindings for placement tests | gatecat | 2021-04-15 | 2 | -0/+8 |
| | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
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index : iCE40/nextpnr | |
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