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* ecp5: Fix derivation of OSCG timing constraintDavid Shah2020-06-291-1/+5
* placer1: Unlock even if placement failsDavid Shah2020-06-291-0/+2
* Make python bindings consistentMiodrag Milanovic2020-06-272-2/+4
* Fix clangformat and execute itMiodrag Milanovic2020-06-275-27/+23
* Update git ignore locationsMiodrag Milanovic2020-06-273-3/+4
* Update some URLsDavid Shah2020-06-262-5/+5
* Merge pull request #460 from whitequark/better-embedDavid Shah2020-06-2621-341/+266
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| * Simplify and improve chipdb embedding/loading.whitequark2020-06-2621-341/+266
* | Update COPYINGDavid Shah2020-06-251-6/+6
* | HeAP: Add timeout to IO placementDavid Shah2020-06-251-0/+4
* | Fix typowhitequark2020-06-251-1/+1
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* Merge pull request #459 from whitequark/better-chipdbDavid Shah2020-06-2514-293/+362
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| * CMake: require at least version 3.5 (Ubuntu 16.04).whitequark2020-06-254-5/+4
| * CMake: rewrite chipdb handling from ground up.whitequark2020-06-2513-288/+358
| * CMake: only request a CXX compiler.whitequark2020-06-242-2/+2
* | Merge pull request #458 from whitequark/patch-1David Shah2020-06-241-3/+0
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| * Remove dead links from READMEwhitequark2020-06-241-3/+0
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* Merge pull request #457 from whitequark/better-bbaDavid Shah2020-06-243-22/+30
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| * CMake: promote bba to a true subproject.whitequark2020-06-233-22/+30
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* clangformatDavid Shah2020-06-121-12/+6
* Merge pull request #454 from YosysHQ/ecp5-global-placeDavid Shah2020-06-101-2/+44
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| * ecp5: Fix placement of DCCs to guarantee routeabilityDavid Shah2020-06-101-2/+44
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* Merge pull request #452 from smunaut/ice40_shiftreg_div_modeDavid Shah2020-06-021-2/+12
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| * ice40: Add fallback behavior for Extra Cell config bits vectorsSylvain Munaut2020-06-021-1/+11
| * ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODESylvain Munaut2020-06-021-1/+1
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* Merge pull request #447 from whitequark/wasiDavid Shah2020-05-248-20/+108
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| * Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-238-20/+108
* | Merge pull request #440 from YosysHQ/lattice-fixesDavid Shah2020-05-183-0/+28
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| * | ecp5: Disconnect dedicated DCU inputs if connected to constantsDavid Shah2020-05-141-0/+12
| * | ecp5: Improve global routing robustnessDavid Shah2020-05-141-0/+11
| * | ecp5: Don't promote VCC/GND to globals even if connected to clock portDavid Shah2020-05-141-0/+2
| * | lpf: Support // commentsDavid Shah2020-05-141-0/+3
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* | clangformatDavid Shah2020-05-162-4/+4
* | Merge pull request #442 from nategraff-sifive/fix-unsupported-spellingDavid Shah2020-05-143-10/+10
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| * | Fix spelling of 'unsupported'Nathaniel Graff2020-05-133-10/+10
* | | Merge pull request #441 from YosysHQ/eddie/fix_topoMiodrag Milanović2020-05-141-16/+16
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| * | | Fix embarassing use of topographical when meaning topologicalEddie Hung2020-05-141-16/+16
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* | | Merge pull request #439 from edbordin/masterMiodrag Milanović2020-05-141-4/+6
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| * | minor patch for MinGW buildEd Bordin2020-05-141-4/+6
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* | Merge pull request #437 from miek/lvcmos33d-driveDavid Shah2020-05-121-0/+19
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| * | ecp5: Allow setting drive strength for LVCMOS33D IOsMike Walters2020-05-121-0/+19
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* / Add missing --top optionDavid Shah2020-05-091-0/+5
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* Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings'David Shah2020-05-013-6/+125
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| * ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| * No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
| * Further condenseRoss Schlaikjer2020-04-291-11/+10
| * Dedupe clock error checkRoss Schlaikjer2020-04-291-12/+13
| * Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-293-40/+46
| * Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
| * Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
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