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* ecp5: Remove obsolete db entries, add Bel z-positionDavid Shah2018-07-232-19/+2
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
* Added Bel port info to GUIMiodrag Milanovic2018-07-221-0/+8
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-226-94/+40
* Move to new apiMiodrag Milanovic2018-07-221-12/+3
* ecp5: Adding new Bel pin APIDavid Shah2018-07-223-3/+63
* ecp5: Fix regression following router updateDavid Shah2018-07-222-2/+2
* Add Arch::getBelPins() to generic and iCE40 archsClifford Wolf2018-07-224-0/+25
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-223-4/+57
* Add Arch::getBelPinType() and Arch::getWireBelPins() in generic archClifford Wolf2018-07-222-2/+12
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-2212-26/+26
* Move common patterns from router1 to Context APIClifford Wolf2018-07-223-150/+124
* clangformatClifford Wolf2018-07-225-39/+30
* QTimer::start(std::chrono::duration -> int)Sergiusz Bazanski2018-07-212-3/+3
* Merge branch 'q3k/lock-2-electric-boogaloo' into 'master'Clifford Wolf2018-07-217-161/+397
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| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Sergiusz Bazanski2018-07-2122-682/+1466
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| * | Re-enable drawing Pips.Sergiusz Bazanski2018-07-201-3/+3
| * | Use UI lock for yieldingSergiusz Bazanski2018-07-204-14/+40
| * | clang-formatSergiusz Bazanski2018-07-201-1/+1
| * | Nuke IdStringDBSergiusz Bazanski2018-07-205-50/+41
| * | Remove dead code.Sergiusz Bazanski2018-07-201-2/+0
| * | clang-format and uncomment debugSergiusz Bazanski2018-07-204-45/+39
| * | Move pthread yield hack into BaseCtxSergiusz Bazanski2018-07-203-10/+14
| * | Mix-in Deterministic RNG at Context instead of BaseCtxSergiusz Bazanski2018-07-201-2/+2
| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Sergiusz Bazanski2018-07-2048-825/+754
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| * | | Refactor renderer threadSergiusz Bazanski2018-07-202-27/+64
| * | | WIP.Serge Bazanski2018-07-177-96/+227
| * | | Add basic external locking, lock from P&RSerge Bazanski2018-07-173-0/+40
| * | | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Serge Bazanski2018-07-1725-395/+1211
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| * \ \ \ Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Serge Bazanski2018-07-1516-313/+810
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| * | | | | Refactor RNG out to separate DeterministicRNG classSerge Bazanski2018-07-141-57/+67
| * | | | | Refactor IdString functionality into IdStringDBSerge Bazanski2018-07-145-27/+33
* | | | | | Add Loc constructorsClifford Wolf2018-07-214-17/+10
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* | | | | Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
* | | | | Merge branch 'router1ng' into 'master'Clifford Wolf2018-07-212-87/+341
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| * | | | | Bugfix in router1: Also bind src_wireClifford Wolf2018-07-211-0/+2
| * | | | | Add final sanity check in router1Clifford Wolf2018-07-211-0/+19
| * | | | | Refactoring of router1Clifford Wolf2018-07-212-87/+320
* | | | | | Map ports to netsMiodrag Milanovic2018-07-211-0/+14
* | | | | | create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
* | | | | | add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
* | | | | | Add used cells and attach them to belsMiodrag Milanovic2018-07-211-0/+39
* | | | | | Fix placement bug with VexRiscV reported by John McMasterDavid Shah2018-07-211-2/+3
* | | | | | Assign proper pipsMiodrag Milanovic2018-07-211-9/+27
* | | | | | add only missing netMiodrag Milanovic2018-07-211-3/+6
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* | | | | Fix minor issue in GUI Wire propertiesClifford Wolf2018-07-211-2/+2
* | | | | Change DelayInfo semantics to what we actually needClifford Wolf2018-07-215-16/+38
* | | | | Add getWireDelay APIClifford Wolf2018-07-214-2/+17
* | | | | Fix warnings and statusMiodrag Milanovic2018-07-213-4/+21
* | | | | Made save project work as wellMiodrag Milanovic2018-07-215-11/+46