iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add Python bindings for placement tests	gatecat	2021-04-15	2	-0/+8
*	Merge pull request #678 from acomodi/initial-fasm-generation	gatecat	2021-04-14	21	-71/+136
\|\
\| *	gh-actions: increase python-fpga-interchange tag version	Alessandro Comodi	2021-04-14	1	-1/+1
\| *	interchange: add FASM generation target and clean-up tests	Alessandro Comodi	2021-04-14	20	-70/+135
* \|	Merge pull request #679 from YosysHQ/gatecat/disable-absl	gatecat	2021-04-14	11	-63/+54
\|\ \ \| \|/ \|/\|
\| *	ci: Re-enable abseil for interchange CI	gatecat	2021-04-14	1	-1/+1
\| *	Hash table refactoring	gatecat	2021-04-14	10	-62/+53
\|/
*	Merge pull request #677 from YosysHQ/gatecat/ppip-no-input	gatecat	2021-04-13	1	-14/+35
\|\
\| *	interchange: Allow pseudo-cells with no input pins	gatecat	2021-04-13	1	-14/+35
* \|	Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash	gatecat	2021-04-13	2	-58/+73
\|\ \ \| \|/ \|/\|
\| *	timing: Fix domain init when loops are present	gatecat	2021-04-13	2	-58/+73
\|/
*	Merge pull request #674 from adamgreig/heap-spreader-fix	gatecat	2021-04-12	1	-0/+4
\|\
\| *	HeAP: Skip high-strength cells in both cell loops.	Adam Greig	2021-04-12	1	-0/+4
* \|	Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref	gatecat	2021-04-12	1	-14/+18
\|\ \ \| \|/ \|/\|
\| *	fast_bels: Don't return pointer that might become invalid	gatecat	2021-04-12	1	-14/+18
* \|	clangformat	gatecat	2021-04-12	8	-133/+134
\|/
*	Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc	gatecat	2021-04-09	1	-6/+10
\|\
\| *	interchange: Disambiguate cell and bel pins when creating Vcc ties	gatecat	2021-04-09	1	-6/+10
* \|	Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin	gatecat	2021-04-09	2	-0/+3
\|\ \ \| \|/ \|/\|
\| *	interchange: Pin prjoxide commit	gatecat	2021-04-09	2	-0/+3
\|/
*	Merge pull request #667 from YosysHQ/fix_qt	Miodrag Milanović	2021-04-08	1	-0/+4
\|\
\| *	Add same fix as in issue #373	Miodrag Milanovic	2021-04-08	1	-0/+4
\|/
*	Merge pull request #665 from cr1901/optional-lto	gatecat	2021-04-07	1	-2/+13
\|\
\| *	Add CMake option to enable IPO (enabled by default).	William D. Jones	2021-04-07	1	-2/+13
\|/
*	Merge pull request #659 from litghost/pseudo_pip_fixes	gatecat	2021-04-06	11	-66/+882
\|\
\| *	[interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.	Keith Rothman	2021-04-06	1	-1/+16
\| *	Don't fail-fast for GH actions to allow for easier CI debugging.	Keith Rothman	2021-04-06	1	-0/+3
\| *	[interchange] Remove requirement to have wire_lut.	Keith Rothman	2021-04-06	3	-6/+7
\| *	[interchange] Fix invalid use of local variables due to refactoring.	Keith Rothman	2021-04-06	3	-6/+7
\| *	[interchange] Prevent site router from generating incorrect LUTs.	Keith Rothman	2021-04-06	3	-42/+102
\| *	[interchange] Scale edge cost of pseudo pips.	Keith Rothman	2021-04-06	2	-5/+12
\| *	[interchange] Fix missing inline methods in site_arch.impl.h	Keith Rothman	2021-04-06	2	-8/+9
\| *	[interchange] Disallow site edges during general routing.	Keith Rothman	2021-04-06	2	-5/+23
\| *	[interchange] Add crude pseudo pip model.	Keith Rothman	2021-04-06	6	-7/+717
* \|	Merge pull request #663 from litghost/fix_router2_without_bb	gatecat	2021-04-06	1	-1/+13
\|\\|
\| *	Fix bug in router2 where router may give up too early.	Keith Rothman	2021-04-06	1	-1/+13
\|/
*	Merge pull request #661 from litghost/document_site_router	gatecat	2021-04-06	1	-10/+58
\|\
\| *	[interchange] Add some documentation for the site router.	Keith Rothman	2021-04-05	1	-10/+58
* \|	Merge pull request #662 from litghost/fix_cirrus_ci	gatecat	2021-04-06	1	-1/+1
\|\ \
\| * \|	Increase vCPU to 5 because of cirrus resource limit change.	Keith Rothman	2021-04-05	1	-1/+1
\| \|/
* \|	Merge pull request #657 from acomodi/interchange-counter-multi-board	gatecat	2021-04-06	5	-23/+25
\|\ \ \| \|/ \|/\|
\| *	interchange: counter: testing on multiple boards	Alessandro Comodi	2021-04-01	5	-23/+25
* \|	Merge pull request #658 from litghost/increment_chipdb	gatecat	2021-04-02	5	-5/+14
\|\ \ \| \|/ \|/\|
\| *	[interchange] Update interchange CI for new chipdb change.	Keith Rothman	2021-04-01	2	-3/+2
\| *	[interchange] Update to v6 of FPGA interchange chipdb.	Keith Rothman	2021-04-01	3	-2/+12
\|/
*	Merge pull request #646 from YosysHQ/gatecat/nexus-cmake	gatecat	2021-03-31	15	-133/+385
\|\
\| *	interchange: Fix nexus cmake review comments	gatecat	2021-03-31	4	-16/+11
\| *	ci: Build prjoxide only for LIFCL	gatecat	2021-03-30	2	-7/+8
\| *	interchange: Split xc7 and nexus chipdb cmake	gatecat	2021-03-30	3	-243/+245
\| *	interchange: Add Nexus LUT test	gatecat	2021-03-30	8	-20/+140